L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

4.3.1.1. Resetting the Transmitter After Power Up

The FPGA automatically calibrates the PLL at every power-up before entering user-mode. Perform a reset sequence after the device enters the user-mode. Your user coded Reset Controller must comply with the reset sequence below to ensure a reliable transmitter initialization after the initial power-up calibration.

The step numbers in this list correspond to the numbers in the following figure.

  1. Deassert tx_analogreset after the device enters user mode for a minimum duration of 2 ms. The CONF_DONE pin is asserted when the device enters user mode.
  2. Wait for tx_analogreset_stat signal from the PHY to deassert, to ensure that tx_analogreset deasserts successfully.
  3. Wait for pll_locked to assert.
  4. Deassert tx_digitalreset after the pll_locked stays asserted for a minimum duration of ttx_digitaltreset .
  5. Wait for tx_digitalreset_stat signal from the PHY, to deassert, to ensure that tx_digitalreset deasserts successfully.
Figure 174. Transmitter Power Up Sequence During device Operation

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