L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

2.4.3.1.1. Primary Use Model

To support higher speed transfer rates and the new EMIB fabric introduced between the FPGA fabric and the L-Tile/H-Tile, Intel® Stratix® 10 devices replace the traditional register mode transfer used for deterministic latency (CPRI, IEEE 1588) with a set of phase compensation FIFOs that allow you to measure its delay. The phase compensation FIFOs include:

  • TX PCS FIFO
  • TX Core FIFO
  • RX PCS FIFO
  • RX Core FIFO

The TX PCS and Core FIFOs comprise the PCS-Core Interface on the TX side. Similarly, the RX PCS and Core FIFOs comprise the PCS-Core interface on the RX side.

Figure 82. PCS-Core Port Interface

The Intel® Stratix® 10 L-Tile/H-Tile Transceiver Native PHY IP core allows you to configure all these FIFOs in phase compensation mode for deterministic latency applications (CPRI, IEEE1588 etc.,). It provides the following ports to measure latency through the TX PCS FIFO, TX Core FIFO, RX PCS FIFO, and RX Core FIFO, respectively:

  • tx_pcs_fifo_latency_pulse
  • tx_fifo_latency_pulse
  • rx_pcs_fifo_latency_pulse
  • rx_fifo_latency_pulse
  • latency_sclk

You must select the Enable latency measurement ports option in the Latency Measurement Ports section of the PCS-Core Interface panel of the Intel® Stratix® 10 L-Tile/H-Tile Transceiver Native PHY IP core, to enable these ports. All ports with the exception of latency_sclk are output ports. The latency_sclk port is an input to the Intel® Stratix® 10 H-Tile Transceiver Native PHY IP core. Set the four FIFOs in phase compensation mode.

The four FIFOs associated with the PCS-Core interface allow for measurement of their latency to sub-cycle accuracy. Each FIFO can output a latency_pulse that is 1 or 0, proportional to how full the FIFO is. For example, if there is a FIFO that is 8 words deep and the FIFO is 4.5 words full, the latency_pulse is a 1 (4.5/8) = 56% of the time.

Figure 83. Phase-measuring FIFO

This measurement pulse is sampled via a sample_clock that can run up to 262 MHz. Meta-stable hardening to this clock is done within the hard logic.

Note: Refer to Deterministic Latency for more information about how to calculate latency across FIFOs.
Figure 84. Phase-measuring FIFO Block Diagram

To measure the fullness of the FIFO, you must run your sampling clock at a rate that is not equal to the parallel clock. For example, parallel_clock * (128/127) or parallel_clock * (64/127) so that the sampling clock sweeps various phase relationships relative to the parallel clock. You must determine via a simple counter how often the resulting pulse is a 1 versus a 0.

The phase measuring circuit is designed to work in the case of a phase compensation FIFO and in the case of a phase compensation FIFO where the read and write pointers may have an exact 2:1 ratio.

The Intel® Stratix® 10 L-Tile/H-Tile Transceiver Native PHY IP core shows you the default maximum depth of the FIFO for the mode chosen.

Table 90.  Potential Depths for Each FIFOThese are the possible depths of each FIFO, and not the default spacing of the counters. The depth selected depends on the mode of the FIFO. When in a 1:2 or a 2:1 mode, depth should be defined as the maximum value that the counter may take for the 2x clock.
FIFO Modes Description
TX Core FIFO (FPGA Fabric side)

8 words deep

16 words deep

32 words deep

Refer to the System Messages of Native PHY IP core to determine the default FIFO depth based on the mode/configuration selected in the IP GUI.
TX PCS FIFO (transceiver side)

8 words deep

16 words deep

Refer to the System Messages of Native PHY IP core to determine the default FIFO depth based on the mode/configuration selected in the IP GUI.
RX PCS FIFO (transceiver side)

8 words deep

16 words deep

Refer to the System Messages of Native PHY IP core to determine the default FIFO depth based on the mode/configuration selected in the IP GUI.
RX Core FIFO (FPGA Fabric side)

8 words deep

16 words deep

64 words deep

Refer to the System Messages of Native PHY IP core to determine the default FIFO depth based on the mode/configuration selected in the IP GUI.

Refer to the FIFO Latency Calculation section for details about usage and examples of the deterministic latency port.

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