To support higher speed transfer rates and the new EMIB fabric introduced between the FPGA fabric and the L-Tile/H-Tile, Intel® Stratix® 10 devices replace the traditional register mode transfer used for deterministic latency (CPRI, IEEE 1588) with a set of phase compensation FIFOs that allow you to measure its delay. The phase compensation FIFOs include:
- TX PCS FIFO
- TX Core FIFO
- RX PCS FIFO
- RX Core FIFO
The TX PCS and Core FIFOs comprise the PCS-Core Interface on the TX side. Similarly, the RX PCS and Core FIFOs comprise the PCS-Core interface on the RX side.
Figure 82. PCS-Core Port Interface