L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

2.4.2.10. Double Rate Transfer Mode

Enable the double rate transfer mode option located in the Datapath Options tab in the Native PHY IP core to:

  • Take advantage of the higher speeds of the Hyperflex architecture in the Intel® Stratix® 10 fabric core
  • Achieve a comparative reduction of IP resource counts with similar IP cores

Double rate transfer means that the data width from the TX PCS FIFO to the PMA is double the data width coming from the FPGA fabric through the EMIB to the TX PCS FIFO. The write clock frequency is double the read clock of the TX PCS FIFO. Whereas the data width from FPGA Fabric to the TX Core FIFO is the same as the data width from the TX Core FIFO to the EMIB. The read and write clock frequencies of the TX Core FIFO are the same. At the RX side, the data width from the PMA to the RX PCS FIFO is double the data width coming from the RX PCS FIFO to the EMIB. The RX PCS FIFO read clock frequency is double the frequency of the write clock. Whereas the data width from the EMIB to the RX Core FIFO is the same as the data width from the RX Core FIFO to the FPGA Fabric. The read and write clock frequencies of the RX Core FIFO are the same.

When this mode is enabled, the PCS parallel data is split into two words. Each word is transferred to and from the transceiver at twice the parallel clock frequency. You can enable the double rate transfer mode for almost all configurations except for the following:

  • PCS FIFO data width ≤ 10 bit
  • Core FIFO data width ≤ 10 bit

When double rate transfer mode is enabled, select PCS clkout x2 in the TX Clock Options and RX Clock Options in the PCS-Core Interface tab of the Native PHY IP Parameter Editor. There is one exception. When using the TX standard PCS with PMA or PCS data width = 20 and byte-serializer = OFF, set PCS_clk_2x = x1, and you must provide a x2 clock generated from the fPLL to drive tx_coreclkin2 for double rate transfer. There is a checkbox you can select, which enables this port on the IP Parameter Editor.

Figure 81. Double Rate Transfer Mode Clocking and Datapath

Disabling or enabling double rate transfer mode changes the parallel data mapping. Refer to the Transceiver PHY PCS-to-Core Interface Reference Port Mapping section for detailed data mapping information.

Did you find the information on this page useful?

Characters remaining:

Feedback Message