L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

3.1.2.2. fPLL IP Core Constraints

To implement the fPLL IP core, you must adhere to the following constraints:

  • You must use create_clock constraints on fPLL reference clocks on the project's top-level SDC file.
  • Any SDC design constraints referring to transceiver clocks must be listed after the transceiver Native PHY SDC file constraints.
  • fPLL output clocks have no phase relationship to the reference clock when utilizing the fPLL output clocks for core usage. The fPLL output clocks of the clock divider are still in phase with each other, however.

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