L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

4.3.1.6.2. Double Rate Transfer Mode enabled

While using Transceiver PHY Reset Controller Intel® Stratix® 10 FPGA IP, if you enable Double Rate Transfer Mode, you must account for the following two cases:
  • TX Core FIFO in Phase Compensation Mode
  • TX Core FIFO in Basic Mode

TX Core FIFO in Phase Compensation Mode

  1. Deassert tx_digitalreset after PLL has acquired lock.
  2. Start to toggle the word marking bit tx_parallel_data[39] until tx_digitalreset_stat is deasserted.
  3. Wait for tx_digitalreset_stat signal from the PHY to deassert, to ensure that tx_digitalreset deasserts successfully.

TX Core FIFO in Basic Mode

  1. Deassert tx_digitalreset after pll has acquired lock.
  2. Start to toggle the word marking bit tx_parallel_data[39].
  3. Wait for tx_dll_lock (from Transceiver Native PHY), to assert.
  4. Assert tx_fifo_wr_en after tx_dll_lock is asserted.
  5. Wait for tx_digitalreset_stat signal from the PHY to deassert, to ensure that tx_digitalreset deasserts successfully.

Did you find the information on this page useful?

Characters remaining:

Feedback Message