L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

2.3.14. Enhanced PCS Ports

Figure 28. Enhanced PCS InterfacesThe labeled inputs and outputs to the PMA and PCS modules represent buses, not individual signals.

In the following tables, the variables represent these parameters:

  • <n>—The number of lanes
  • <d>—The serialization factor
  • <s>— The symbol size
  • <p>—The number of PLLs
Table 60.  Interlaken Frame Generator, Synchronizer, and CRC32
Name Direction Clock Domain Description
tx_enh_frame[<n>-1:0] Output

tx_clkout

Asserted for 2 or 3 parallel clock cycles to indicate the beginning of a new metaframe.

tx_err_ins Input tx_coreclkin

For the Interlaken protocol, you can use this bit to insert the synchronous header and CRC32 errors if you have turned on Enable simplified data interface.

When asserted, the synchronous header for that cycle word is replaced with a corrupted one. A CRC32 error is also inserted if Enable Interlaken TX CRC-32 generator error insertion is turned on. The corrupted sync header is 2'b00 for a control word, and 2'b11 for a data word. For CRC32 error insertion, the word used for CRC calculation for that cycle is incorrectly inverted, causing an incorrect CRC32 in the Diagnostic Word of the Metaframe.

Note that a synchronous header error and a CRC32 error cannot be created for the Framing Control Words because the Frame Control Words are created in the frame generator embedded in TX PCS. Both the synchronous header error and the CRC32 errors are inserted if the CRC-32 error insertion feature is enabled in the Transceiver Native PHY IP Core GUI.

tx_dll_lock Output tx_clkout User should monitor this lock status when the TX Core FIFO is configured in Interlaken or Basic mode of operation.

For tx_dll_lock timing diagrams, refer to the Special TX PCS Reset Release Sequence under Resetting Transceiver Channels chapter.

.
tx_enh_frame_diag_status[2<n>-1:0]

Input

tx_clkout

Drives the lane status message contained in the framing layer diagnostic word (bits[33:32]). This message is inserted into the next diagnostic word generated by the frame generator block. This bus must be held constant for 5 clock cycles before and after the tx_enh_frame pulse. The following encodings are defined:

  • Bit[1]: When 1, indicates the lane is operational. When 0, indicates the lane is not operational.
  • Bit[0]: When 1, indicates the link is operational. When 0, indicates the link is not operational.
tx_enh_frame_burst_en[<n>-1:0]

Input

tx_clkout

If Enable frame burst is enabled, this port controls frame generator data reads from the TX FIFO to the frame generator. It is latched once at the beginning of each Metaframe. If the value of tx_enh_frame_burst_en is 0, the frame generator does not read data from the TX FIFO for current Metaframe. Instead, the frame generator inserts SKIP words as the payload of Metaframe. When tx_enh_frame_burst_en is 1, the frame generator reads data from the TX FIFO for the current Metaframe. This port must be held constant for 5 clock cycles before and after the tx_enh_frame pulse.

rx_enh_frame[<n>-1:0]

Output

rx_clkout

When asserted, indicates the beginning of a new received Metaframe. This signal is pulse stretched.

rx_enh_frame_lock[<n>-1:0]

Output

rx_clkout

SSR16

When asserted, indicates the Frame Synchronizer state machine has achieved Metaframe delineation. This signal is pulse stretched.

rx_enh_frame_diag_status[2 <n>-1:0]

Output

rx_clkout

SSR16

Drives the lane status message contained in the framing layer diagnostic word (bits[33:32]). This signal is latched when a valid diagnostic word is received in the end of the Metaframe while the frame is locked. The following encodings are defined:

  • Bit[1]: When 1, indicates the lane is operational. When 0, indicates the lane is not operational.
  • Bit[0]: When 1, indicates the link is operational. When 0, indicates the link is not operational.
rx_enh_crc32_err[<n>-1:0]

Output

rx_clkout

FSR16

When asserted, indicates a CRC error in the current Metaframe. Asserted at the end of current Metaframe. This signal gets asserted for 2 or 3 cycles.

Table 61.  10GBASE-R BER Checker
Name Direction Clock Domain Description
rx_enh_highber[<n>-1:0] Output

rx_clkout

SSR16

When asserted, indicates a bit error rate that is greater than 10 -4. For the 10GBASE-R protocol, this BER rate occurs when there are at least 16 errors within 125 µs. This signal gets asserted for 2 to 3 clock cycles.

rx_enh_highber_clr_cnt[<n>-1:0]

Input

rx_clkout

SSR16

When asserted, clears the internal counter that indicates the number of times the BER state machine has entered the BER_BAD_SH state.
rx_enh_clr_errblk_count[<n>-1:0] (10GBASE-R and FEC)

Input

rx_clkout

SSR16

When asserted the error block counter resets to 0. Assertion of this signal clears the internal counter that counts the number of times the RX state machine has entered the RX_E state. In modes where the FEC block is enabled, the assertion of this signal resets the status counters within the RX FEC block.

Table 62.  Block Synchronizer
Name Direction Clock Domain Description
rx_enh_blk_lock<n>-1:0] Output

rx_clkout

SSR16

When asserted, indicates that block synchronizer has achieved block delineation. This signal is used for 10GBASE-R and Interlaken.
Table 63.  Gearbox
Name Direction Clock Domain Description
rx_bitslip[<n>-1:0] Input

rx_clkout

SSR16

The rx_parallel_data slips 1 bit for every positive edge of the rx_bitslip input. Keep the rx_bitslip pulse high for at least 200 ns and each pulse 400 ns apart to ensure the data is slipped. The maximum shift is < pcswidth -1> bits, so that if the PCS is 64 bits wide, you can shift 0-63 bits.

tx_enh_bitslip[<n>-1:0] Input rx_clkout

SSR16

The value of this signal controls the number of bits to slip the tx_parallel_data before passing to the PMA.

Table 64.  KR-FEC
Name Direction Clock Domain Description
tx_enh_frame[<n>-1:0] Output

Asynchronous

Asynchronous status flag output of TX KR-FEC that signifies the beginning of generated KR FEC frame
rx_enh_frame[<n>-1:0] Output rx_clkout

SSR16

Asynchronous status flag output of RX KR-FEC that signifies the beginning of received KR FEC frame
rx_enh_frame_diag_status[2<n>-1:0] Output rx_clkout

SSR16

Asynchronous status flag output of RX KR-FEC that indicates the status of the current received frame.

  • 00: No error
  • 01: Correctable Error
  • 10: Un-correctale error
  • 11: Reset condition/pre-lock condition
16 For a detailed description of FSR and SSR signals, please go to the Asynchronous Data Transfer section.

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