L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

4.5.2. Transceiver PHY Reset Controller Intel® Stratix® 10 FPGA IP Parameters

The Intel® Quartus® Prime Pro Edition software provides a GUI to define and instantiate a Transceiver PHY Reset Controller Intel® Stratix® 10 FPGA IP to reset transceiver PHY.

Table 145.  General Options
Name Range Description
Tile Type of Native PHY IP L-Tile ES, L-Tile Production / H-Tile Specifies the tile type to which the Reset Controller is connected.
Number of transceiver channels 1-1000 Specifies the number of channels that connect to the Transceiver PHY Reset Controller Intel® Stratix® 10 FPGA IP. The upper limit of the range is determined by your FPGA architecture.
Number of TX PLLs 1-1000 Specifies the number of TX PLLs that connect to the Transceiver PHY Reset Controller Intel® Stratix® 10 FPGA IP.
Input clock frequency 1-500 MHz Input clock to the Transceiver PHY Reset Controller Intel® Stratix® 10 FPGA IP. The frequency of the input clock in MHz. The upper limit on the input clock frequency is the frequency achieved in timing closure.
Use fast reset for simulation On /Off

When On, the Transceiver PHY Reset Controller Intel® Stratix® 10 FPGA IP uses reduced reset counters for simulation.

Therefore, the reset behavior in simulation and hardware are different when you enable this option.

Sequence RX digital reset after TX digital reset On /Off

When On, the IP staggers the deassertion of TX digital reset before RX digital reset (i.e TX digital reset deassertion gates RX digital reset deassertion) . Typically this is used for PIPE application where TX PCS must be out of reset before RX PCS.

Separate interface per channel/PLL On /Off When On, the Transceiver PHY Reset Controller Intel® Stratix® 10 FPGA IP provides a separate reset interface for each channel and PLL.
TX Channel
Enable TX channel reset control On /Off When On, the Transceiver PHY Reset Controller Intel® Stratix® 10 FPGA IP enables the control logic and associated status signals for TX reset. When Off, disables TX reset control and status signals.
Use separate TX reset per channel On /Off When On, each TX channel has a separate reset. When Off, the Transceiver PHY Reset Controller Intel® Stratix® 10 FPGA IP uses a shared TX reset controller for all channels.
TX digital reset mode Auto, Manual Specifies the Transceiver PHY Reset Controller Intel® Stratix® 10 FPGA IP behavior when the pll_locked signal is deasserted. The following modes are available:
  • Auto—The associated tx_digitalreset controller automatically resets whenever the pll_locked signal is deasserted. Intel recommends this mode.
  • Manual—The associated tx_digitalreset controller is not reset when the pll_locked signal is deasserted, allowing you to choose corrective action.
tx_analogreset duration 1-999999999

Specifies the time in ns (ttx_analogreset) to continue to assert tx_analogreset after the reset input and all other gating conditions are removed. The value is rounded up to the nearest clock cycle. The Transceiver PHY Reset Controller Intel® Stratix® 10 FPGA IP shows a default value.

tx_digitalreset duration 1-999999999 Specifies the time in ns (ttx_digitalreset) to continue to assert the tx_digitalreset after the reset input and all other gating conditions are removed. The value is rounded up to the nearest clock cycle. The Transceiver PHY Reset Controller Intel® Stratix® 10 FPGA IP shows a default value.
pll_locked input hysteresis 0-999999999 Specifies the amount of hysteresis in ns to add to the pll_locked status input to filter spurious unreliable assertions of the pll_locked signal. A value of 0 adds no hysteresis. A higher value filters glitches on the pll_locked signal. Intel recommends that the amount of hysteresis be longer than tpll_lock_max_time.
Enable pll_cal_busy input port On/ Off When On, the Transceiver PHY Reset Controller Intel® Stratix® 10 FPGA IP enables/ exposes the pll_cal_busy input port. When Off, disables pll_cal_busy input port.
RX Channel
Enable RX channel reset control On /Off When On, each RX channel has a separate reset input. When Off, each RX channel uses a shared RX reset input for all channels. This implies that if one of the RX channels is not locked, all other RX channels are held in reset until all RX channels are locked. Digital reset stays asserted until all RX channels have acquired lock.
Use separate RX reset per channel On /Off When On, each RX channel has a separate reset input. When Off, uses a shared RX reset controller for all channels.
RX digital reset mode Auto, Manual Specifies the Transceiver PHY Reset Controller Intel® Stratix® 10 FPGA IP behavior when the PLL lock signal is deasserted. The following modes are available:
  • Auto—The associated rx_digitalreset controller automatically resets whenever the rx_is_lockedtodata signal is deasserted.
  • Manual—The associated rx_digitalreset controller is not reset when the rx_is_lockedtodata signal is deasserted, allowing you to choose corrective action.
rx_analogreset duration 1-999999999 Specifies the time in ns to continue to assert the rx_analogreset after the reset input and all other gating conditions are removed. The value is rounded up to the nearest clock cycle. The default value is 40 ns.
rx_digitalreset duration 1-999999999 Specifies the time in ns to continue to assert the rx_digitalreset after the reset input and all other gating conditions are removed. The value is rounded up to the nearest clock cycle. The default value is 5000 ns.

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