L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 2/20/2023
Public
Document Table of Contents

3.1.1.1. ATX PLL to fPLL Spacing Requirements

When using ATX PLLs and fPLLs operating at the same VCO frequency or within 100 MHz, you must observe the spacing requirements listed in the following table. This rule applies to fPLLs in both transceiver mode and core mode.

Table 126.  ATX PLL to fPLL Spacing Requirements
ATX PLL to fPLL Spacing Spacing Requirement
ATX PLL to fPLL spacing
  • Skip 1 ATX PLL when ATX PLL and fPLL VCO frequencies are within 100 MHz and the fPLL's L counter = 1

OR

  • None if fPLL L counter ≥ 243

There is no ATX PLL placement restriction between two different tiles.

Figure 141. ATX PLL to fPLL Placement Example
43 You can find the L Counter value in the Advanced Parameter tab of the fPLL IP.

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