L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

6.14. Timing Closure Recommendations

You must close timing for the reconfiguration profiles in the following cases:
  1. When the multiple reconfiguration profile is not enabled. You must manually include constraints for all the modified and target configuration. See example below:
    Figure 246. Multiple Reconfiguration Profile Not Enabled
  2. When the multiple reconfiguration profile is enabled, and

    Case 1: More than 8 configurations are required:

    When you have exhausted maximum configurations (eight) supported by Native PHY IP. You must manually include constraints for all the modified and target configuration outside of the 8 configurations supported by the Native PHY IP.
    Figure 247. Multiple Reconfiguration Profile is Enabled (n=8)

    Case 2: Some configurations are generated with Multiple Reconfiguration Profile disabled.

    Figure 248. 
Note: Native PHY IP, supports up to eight reconfiguration profiles and generates appropriate SDC constraints for all paths.

Intel recommends that you enable the multiple reconfiguration profiles feature in the Native PHY IP core if any of the modified or target configurations involve changes to PCS settings.

Using multiple reconfiguration profiles is optional if the reconfiguration involves changes to only PMA settings such as PLL switching, CGB divider switching, and refclk switching.

When supporting dynamic reconfiguration, you must:

  • Include constraints to create the extra clocks for all modified or target configurations at the PCS-FPGA fabric interface. Clocks for the base configuration are created by the Quartus Prime software. These clocks enable the Intel® Quartus® Prime Pro Edition to perform static timing analysis for all the transceiver configuration profiles and their corresponding FPGA fabric core logic blocks.
  • Include the necessary false paths between the PCS – FPGA fabric interface and the core logic.

For example, you can perform dynamic reconfiguration to switch the datapath from Standard PCS to Enhanced PCS using the multiple reconfiguration profiles feature. In the following example, the base configuration uses the Standard PCS (data rate = 1.25 Gbps, PCS-PMA width = 10) and drives core logic A in the FPGA fabric. The target or modified configuration is configured to use the Enhanced PCS (data rate = 12.5 Gbps, PCS-PMA width = 64) and drives core logic B in the FPGA fabric.

Figure 249. Using Multiple Reconfiguration Profiles
In the above example, you must
  • create the tx_clkout clock that is used to clock the core logic B in the FPGA fabric.
  • Based on how the clocks are connected in the design, you might have to include additional constraints to set false paths from the registers in the core logic to the clocks. For example,
    set_false_path -from [get_clocks {tx_clkout_enh}] -to [get_registers <Core Logic A>]
    set_false_path -from [get_clocks {rx_clkout_enh}] -to [get_registers <Core Logic A>] 
    set_false_path -from [get_clocks {tx_clkout}] -to [get_registers <Core Logic B>]
    set_false_path -from [get_clocks {rx_clkout}] -to [get_registers <Core Logic B>]

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