L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

2.4.4.1.4. PRBS Control and Status Ports

Within the RX PMA tab of the Native PHY IP core, you can enable the following control and status ports to use the internal PRBS verifier:

  • rx_prbs_done—Indicates the PRBS sequence has completed one full cycle. It stays high until you reset it with rx_prbs_err_clr.
  • rx_prbs_err—Goes high if an error occurs. This signal is pulse-extended to allow you to capture it in the RX FPGA CLK domain.
  • rx_prbs_err_clr—Used to reset the rx_prbs_err signal.

Refer to RX PMA Ports for more details on their functions. Refer to the Transceiver PHY PCS-to-Core Interface Port Mapping section for the exact bit location. Refer to the Asynchronous Data Transfer section for requirements on these signals when simplified interface is not enabled.

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