L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 10/05/2023
Document Table of Contents How to Place Channels for PIPE Configurations

The following restrictions apply when placing channels for PIPE configurations:

  • The channels must be contiguous because PCIe requires bonded channels.
  • The master CGB is the only way to access the x6 lines, and you must use it in bonded designs (x2, x4, x8 and x16). You cannot use the local CGB to route clock signals to slave channels because the local CGB does not have access to x6 lines.
  • The logical PCS master channel in the bonded configurations must align with physical channel 1 or 4 of the bank. Refer to the Master Channel in Bonded Configurations section for more details.

For ATX PLL placement restrictions, refer to the "Transmit PLL Recommendations Based on Data Rates" section of the PLLs and Clock Networks chapter.