L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 1/30/2024
Document Table of Contents

6.9.1. Switching Transmitter PLL

Dynamically switching data rates increases system flexibility to support multiple protocols. You can change the transceiver channel data rate by switching from one transmit PLL to another. To switch between transmit PLLs, you must reconfigure the local CGB MUX select lines of the channel by performing a channel reconfiguration. You can clock transceiver channels with up to four different transmitter PLLs. You can use the reconfiguration interface on the Native PHY IP core to specify which PLL drives the transceiver channel. The PLL switching method is the same, regardless of the number of transmitter PLLs involved.

Before initiating the PLL switch procedure, ensure that your Transceiver Native PHY instance defines more than one transmitter PLL input. Specify the Number of TX PLL clock inputs per channel parameter on the TX PMA tab during Transceiver Native PHY parameterization.

Refer to Logical View of the L-Tile/H-Tile Transceiver Registers for details on the registers and bits. The number of exposed tx_serial_clk bits varies according to the number of transmitter PLLs you specify. Use the Native PHY reconfiguration interface for this operation.

Table 159.  Lookup Registers for Transmit PLL switching
Transceiver Native PHY Port Description Address Bits
tx_serial_clk0 Represents logical PLL0. Lookup register x117[3:0] stores the mapping from logical PLL0 to the physical PLL. 0x117 (Lookup Register) [3:0]
tx_serial_clk1 Represents logical PLL1. Lookup register x117[7:4] stores the mapping from logical PLL1 to the physical PLL. 0x117 (Lookup Register) [7:4]
tx_serial_clk2 Represents logical PLL2. Lookup register x118[3:0] stores the mapping from logical PLL2 to the physical PLL. 0x118 (Lookup Register) [3:0]
tx_serial_clk3 Represents logical PLL3. Lookup register x118[7:4] stores the mapping from logical PLL3 to the physical PLL. 0x118 (Lookup Register) [7:4]
N/A PLL selection MUX 0x111 [7:0]

When performing a PLL switch, you must specify the lookup register address and bit values you want to switch to. The following procedure describes selection of a specific transmitter PLL when more than one PLL is connected to a channel. To change the data rate of the CDR, follow the detailed steps for reconfiguring channel and PLL blocks. After determining the logical PLL to switch to, follow this procedure to switch to the desired transmitter PLL:

  1. Perform the necessary steps from steps 1 to 10 in Steps to Perform Dynamic Reconfiguration.
  2. Read from the appropriate lookup register address and save the required 4-bit pattern. For example, switching to logical PLL1 requires saving bits [7:4] of address 0x117.
  3. Encode the 4-bit value read in the previous step into an 8-bit value according to the following table:
    Table 160.  Logical PLL Encoding
    4-bit Logical PLL Bits 8-bit Mapping to Address 0x111
    [3..0] {~logical_PLL_offset_readdata[3], logical_PLL_offset_readdata[1:0],logical_PLL_offset_readdata[3], logical_PLL_offset_readdata[3:0] }
    [7..4] {~logical_PLL_offset_readdata[7], logical_PLL_offset_readdata[5:4],logical_PLL_offset_readdata[7], logical_PLL_offset_readdata[7:4] }
    Note: For example, if reconfiguring to logical PLL1 then bits [7:4] are encoded to an 8-bit value {~bit[7], bit[5:4], bit[7], bit[7:4]}.
  4. Perform a read-modify-write to bits[7:0] of address 0x111 using the encoded 8-bit value.
    Note: The bits [6:5] of address 0x111 decoded from Step 3. can be ignored whenever bit [7] is set to 1. For example, if your encoded 8-bit value from the equation stated in Logical PLL Encoding is 0xA1, it translates to 3'b101 for bits [7:5]. Even though the decoded 3-bit value is 3’b101, the value 3’b100 is used and in this case the local CGB setting is selected. See Transmitter PLL Switching Register Map for more information.
  5. Perform the necessary steps from steps 12 to 14 in Steps to Perform Dynamic Reconfiguration.
Figure 240. TX PLL Switching