L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

4.6. Using a User-Coded Reset Controller

You can design your own user-coded reset controller instead of using Transceiver PHY Reset Controller Intel® Stratix® 10 FPGA IP. Your user-coded reset controller must provide the following functionality for the recommended reset sequence:
  • A clock signal input for your reset logic
  • Holds the transceiver channels in reset by asserting the appropriate reset control signals
  • Checks the PLL status (for example, checks the status of pll_locked and pll_cal_busy)

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