L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

4.3.1.6.3. TX Gearbox Ratio *:67

When Enhanced PCS gearbox is enabled with gearbox ratio of *:67 in TX channel, TX PCS reset release is handled differently.

Make sure you have enabled the rcfg_tx_digitalreset_release_ctrl port on Intel® Stratix® 10 L-Tile/H-Tile Transceiver Native PHY, under Dynamic Reconfiguration options, if you intend to dynamically reconfigure to/from gearbox ratio *:67 (i.e 32:67, 40:67 and 64:67). To ensure that transceiver channels are ready to transmit data, you must properly reset the transceiver PHY.

Configuring to *:67 Gearbox ratio

  • With Intel® Stratix® 10 Reset Controller IP

    When configuring to gearbox ratio of *:67, deassert the rcfg_tx_digitalreset_ctrl port 30ns before you deassert the reset input of reset controller IP.

  • With User Code Reset Controller

    When configuring to gearbox ratio of *:67, deassert the rcfg_tx_digitalreset_release_ctrl port 30ns before you deassert the tx_digitalreset.

Configuring from *:67 Gearbox Ratio

  • With Intel® Stratix® 10 Reset Controller IP

    When configuring from gearbox ratio of *:67 to another mode, assert the rcfg_tx_digitalreset_release_ctrl port 30ns before you deassert the reset input of reset controller IP.

  • With User Code Reset Controller

    When configuring from gearbox ratio of *:67 to another mode, assert the rcfg_tx_digitalreset_release_ctrl port 30ns before you deassert the tx_digitalreset.

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