L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

5.1.1.2. Transmitter Buffer

The transmitter buffer includes the following circuitry:

  • High Speed Differential I/O
  • Programmable differential output voltage (VOD)
  • Programmable two tap pre-emphasis circuitry with pre-tap and post-tap polarity
    • One pre-cursor tap
    • One post-cursor tap
  • Slew rate control
  • Internal termination circuitry
  • Electrical idle to support PCI Express configuration
Figure 186. Transmitter Buffer

Did you find the information on this page useful?

Characters remaining:

Feedback Message