L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 1/30/2024
Document Table of Contents

7.5.10. Recalibrating the CMU PLL When it is Used as a TX PLL

Note: Address refers to the simplex RX channel offset address.

Disable background calibration if you have it on.

  1. Write 0x0 to channel offset address 0x542[0] to disable background calibration.
    You have control if 0x542[0] = 0x0 or 0x481[2] = 0x0 or if reconfig_waitrequest is low.


  1. Perform a RMW operation on 0x01 with mask 0x01 to address 0x100. This sets the CMU PLL calibration enable bits.
  2. Write 0x01 to address 0x00. This lets the PreSICE perform the calibration.
  3. Loop read 0x480[1] until you see the bit become 0x0.
    • CMU PLL calibration is complete when 0x480[1] = 0x0.

Enable background calibration.

  1. Write 0x1 to channel offset address 0x542[0].