L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Document Table of Contents Reference Clock I/O Standard

Pin Planner or Assignment Editor Name: I/O Standard

Description: The I/O Standard dictates the type of interface standard used on the pins.

Syntax for QSF Setting:

set_instance_assignment -name IO_STANDARD <value> -to <dedicated refclk pin name>

Table 139.  Available Options
Value Description
High Speed Current Steering Logic (HCSL) High Speed Current Steering Logic (HCSL) is the recommended differential I/O standard for PCI Express applications. It is an open emitter output with a 15 mA current source and requiring 50 Ω external resistor to ground for the output to be switching. In the PCI Express configurations, DC-coupling is allowed on the REFCLK if the selected REFCLK I/O standard is HCSL.
Current Mode Logic (CML) Current mode logic (CML), or source-coupled logic (SCL), is the recommended differential I/O standard intended for data transmission at speeds between 312.5 Mbps & 3.124 Gbps across standard printed circuit boards. The data transmission is point-to-point, unidirectional, and is usually terminated at the destination with 50 Ω on both differential lines. CML is frequently used in interfaces to fiber optic components, connections between modules, HDMI video etc.,
Low Voltage Differential Signaling (LVDS) Low-voltage differential signaling, or LVDS, also known as TIA/EIA-644, is the low power and high speeds as it uses inexpensive twisted-pair copper cables.
Low-Voltage Positive/Pseudo Emitter–Coupled Logic (LVPECL) The LVPECL electrical specification is similar to LVDS, but operates with a larger differential voltage swing. LVPECL is less power efficient than LVDS due to its ECL origins and larger swings.

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