L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

6.13. Embedded Debug Features

The Intel® Stratix® 10 Transceiver Native PHY, ATX PLL, fPLL, and CMU PLL IP cores provide the following optional debug features to facilitate embedded test and debug capability:

  • Native PHY Debug Master Endpoint (NPDME)
  • Optional Reconfiguration Logic

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