L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 10/05/2023
Document Table of Contents

6.13. Embedded Debug Features

The Intel® Stratix® 10 Transceiver Native PHY, ATX PLL, fPLL, and CMU PLL IP cores provide the following optional debug features to facilitate embedded test and debug capability:

  • Native PHY Debug Master Endpoint (NPDME)
  • Optional Reconfiguration Logic