L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

3.2.3. PLL Cascading as an Input Reference Clock Source

In PLL cascading, PLL outputs are connected to the cascading clock network. In this mode, the output of one PLL drives the reference clock input of another PLL. PLL cascading can generate frequency outputs not normally possible with a single PLL solution. The transceivers in Intel® Stratix® 10 devices support fPLL to fPLL cascading. ATX PLL to fPLL cascading is available to OTN and SDI protocols only.
Note:
  • To successfully complete the calibration process, the reference clocks driving the PLLs (ATX PLL, fPLL) must be stable and free running at start of FPGA configuration. Otherwise, recalibration will be necessary.
  • When the fPLL is used as a cascaded fPLL (downstream fPLL), a user recalibration on the fPLL is required. Refer to "User Recalibration" section in "Calibration" chapter for more information.

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