L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

A.3.3. Optional Reconfiguration Logic fPLL-Control & Status

Enables users to read the status of fPLL functions and reset the fPLL.
Name Address Type Attribute Name Encodings
PLL Locked Status

0x480[0]

read-only fpll_pll_locked Indicates if the fPLL is locked. 1'b1 indicates the fPLL is locked.
PLL Calibration Busy Status

0x480[1]

read-only fpll_cal_busy Indicates the fPLL calibration status. 1'b1 indicates the fPLL is currently being calibrated.
Avalon® memory-mapped interface Bus Busy Status

0x480[2]

read-only fpll_avmm_busy Shows the status of internal configuration bus arbitration. When 1'b1, PreSICE has control of the internal configuration bus. When 1'b0, you have control of the internal configuration bus. Refer to the Arbitration section for more details.
PLL Power-down

0x4E0[0]

read-write fpll_pll_powerdown Drives the PLL power-down when the Override is set.
Override PLL Power-down

0x4E0[1]

read-write fpll_override_pll_powerdown Ensures the PLL listens to the NPDME pll_powerdown register. 1'b1 indicates the receiver listens to the NPDME pll_powerdown.

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