L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

6.9.2.2. fPLL Reference Clock Switching

You can use the reconfiguration interface on the fPLL instance to specify which reference clock source drives the fPLL. The fPLL supports clocking by up to five different reference clock sources.

Before initiating a reference clock switch, ensure that your fPLL instance defines more than one reference clock source. Specify the Number of PLL reference clocks parameter on the PLL tab during fPLL parameterization.

The number of exposed pll_refclk ports varies according to the number of reference clocks you specify. Use the fPLL reconfiguration interface for this operation.

Table 162.  Register Map for Switching fPLL Reference Clock Inputs
Transceiver fPLL Port Description Address Bits
pll_refclk0 Represents logical refclk0 for MUX_0. Lookup register x117[4:0] stores the mapping from logical refclk0 to the physical refclk for MUX_0. 0x117 (Lookup Register) [7:0]
pll_refclk1 Represents logical refclk1 for MUX_0. Lookup register x118[4:0] stores the mapping from logical refclk1 to the physical refclk for MUX_0. 0x118 (Lookup Register) [7:0]
pll_refclk2 Represents logical refclk2 for MUX_0. Lookup register x119[4:0] stores the mapping from logical refclk2 to the physical refclk for MUX_0. 0x119 (Lookup Register) [7:0]
pll_refclk3 Represents logical refclk3 for MUX_0. Lookup register x11A[4:0] stores the mapping from logical refclk3 to the physical refclk for MUX_0. 0x11A (Lookup Register) [7:0]
pll_refclk4 Represents logical refclk4 for MUX_0. Lookup register x11B[4:0] stores the mapping from logical refclk4 to the physical refclk for MUX_0. 0x11B (Lookup Register) [7:0]
N/A

fPLL refclk selection MUX_0.

0x114 [7:0]
pll_refclk0 Represents logical refclk0 for MUX_1. Lookup register x11D[4:0] stores the mapping from logical refclk0 to the physical refclk for MUX_1. 0x11D (Lookup Register) [7:0]
pll_refclk1 Represents logical refclk1 for MUX_1. Lookup register x11E[4:0] stores the mapping from logical refclk1 to the physical refclk for MUX_1. 0x11E (Lookup Register) [7:0]
pll_refclk2 Represents logical refclk2 for MUX_1. Lookup register x11F[4:0] stores the mapping from logical refclk2 to the physical refclk for MUX_1. 0x11F (Lookup Register) [7:0]
pll_refclk3 Represents logical refclk3 for MUX_1. Lookup register x120[4:0] stores the mapping from logical refclk3 to the physical refclk for MUX_1. 0x120 (Lookup Register) [7:0]
pll_refclk4 Represents logical refclk4 for MUX_1. Lookup register x121[4:0] stores the mapping from logical refclk4 to the physical refclk for MUX_1. 0x121 (Lookup Register) [7:0]
N/A fPLL refclk selection MUX_1. 0x11C [7:0]

Specify the logical reference clock and respective address and bits of the replacement clock when performing a reference clock switch. Follow this procedure to switch to the selected reference clock:

  1. Perform the necessary steps from steps 1 to 10 in Steps to Perform Dynamic Reconfiguration.
  2. Read from the lookup register for MUX 0 and save the required 8-bit pattern. For example, switching to logical refclk3 requires use of bits[7:0] at address 0x11A.
  3. Perform a read-modify-write to bits [7:0] at address 0x114 using the 8-bit value obtained from the lookup register.
  4. Read from the lookup register for MUX 1 and save the required 8-bit pattern. For example, switching to logical refclk3 requires use of bits[7:0] at address 0x120.
  5. Perform a read-modify-write to bits [7:0] at address 0x11C using the 8-bit value obtained from the lookup register.
  6. Perform the necessary steps from steps 12 to 14 in Steps to Perform Dynamic Reconfiguration.

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