L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

4.4. Using PCS Reset Status Port

Table 144.  PCS Status Reset Port Values for Different Conditions
PCS reset status port Correct Reset Applied No Reset Applied

rx_coreclkin

not connected

tx_coreclkin

not connected

tx_transfer_ready 1 0 1 0
osc_transfer_en 1 1 1 1
tx_digitalreset_timeout 0 0 0 0
tx_fifo_ready 1 1 1 0
rx_transfer_ready 1 0 0 1
rx_digitalreset_timeout 0 0 0 0
rx_fifo_ready 1 0 0 1
tx_digitalreset_stat 0 1 0 1
rx_digitalreset_stat 0 1 1 0

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