L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

1.3.5.3.4. GXT Clock Network

The GXT Clock Network allows the ATX PLL to drive up to six GXT channels in non-bonded mode.

The top ATX PLL in a bank can drive:

  • Channels 0, 1, 3, 4 in the bank
  • Channels 0, 1 in the bank above in the same H-Tile

The bottom ATX PLL in a bank can drive:

  • Channels 0, 1, 3, 4 in the bank
  • Channels 3, 4 in the bank below in the same H-Tile

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