L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

2.5.1.10. ATX PLL Ports for PIPE

Table 114.  ATX PLL Ports for PIPE
Port Direction Clock Domain Description
pll_reflck0 In N/A

Reference clock input port 0. There are five reference clock input ports. The number of reference clock ports available depends on the Number of PLL reference clocks parameter.

tx_serial_clk Out N/A

High speed serial clock output port for GX channels. Represents the x1 clock network.

For Gen1x1, Gen2x1, connect the output from this port to the tx_serial_clk input of the Native PHY IP.

For Gen1x2, x4, x8, x16, use the tx_bonding_clocks output port to connect to the Native PHY IP.

For Gen2x2, x4, x8, x16, use the tx_bonding_clocks output port to connect to the Native PHY IP.

For Gen3x1, connect the output from this port to one of the two tx_serial_clk input ports on the Native PHY IP.

For Gen3x2, x4, x8, x16, this port is not used. Use the tx_serial_clk output from the fPLL to drive the Auxiliary Master CGB clock input port of the ATX PLL.

pll_locked Out Asynchronous

Active high status signal which indicates if PLL is locked.

pll_pcie_clk Out N/A

This is the hclk required for PIPE interface.

For Gen1x1,x2,x4,x8, x16, use this port to drive the hclk for the PIPE interface.

For Gen2x1,x2,x4,x8, x16, use this port to drive the hclk for the PIPE interface.

For Gen3x1,x2,x4,x8, x16, this port is not used. Use the pll_pcie_clk from fPLL (configured as Gen1/Gen2) as the hclk for the PIPE interface.

pll_cal_busy Out Asynchronous

Status signal which is asserted high when PLL calibration is in progress. If this port is not enabled in the Transceiver PHY Reset Controller, then perform logical OR with this signal and the tx_cal_busy output signal from the Native PHY IP core to input the tx_cal_busy on the Transceiver PHY Reset Controller.

mcgb_aux_clk0 In N/A

Used for Gen3 to switch.

between fPLL/ATX PLL during link speed negotiation.

For Gen3x2,x4,x8, x16, use the tx_serial_clk output port from fPLL (configured for Gen1/Gen2) to drive the mcgb_aux_clk input port on the ATX PLL.

tx_bonding_clocks[5:0] Out N/A

Optional 6-bit bus which carries the low speed parallel clock outputs from the Master CGB. Used for channel bonding, and represents the x6/xN clock network.

For Gen1x1, this port is disabled.

For Gen1x2,x4,x8, x16, connect the output from this port to the tx_bonding_clocks input on the Native PHY IP.

For Gen2x1, this port is disabled

For Gen2x2,x4,x8, x16, connect the output from this port to tx_bonding_clocks input on the Native PHY IP.

For Gen3x1, this port is disabled.

For Gen3x2,x4,x8, x16, use the tx_bonding_clocks output from the ATX PLL to connect to the tx_bonding_clocks input of the Native PHY IP.

pcie_sw[1:0] In Asynchronous

2-bit rate switch control input used for PCIe protocol implementation.

For Gen1, this port is N/A.

For Gen 2x2,x4,x8, x16, connect the pipe_sw output from the Native PHY IP to this port.

For Gen3x2,x4,x8, x16, use the pipe_sw output from the Native PHY IP to drive this port.

pcie_sw_done[1:0] Out Asynchronous

2-bit rate switch status output used for PCIe protocol implementation.

For Gen1, this port is N/A.

For Gen2x2, x4, x8, x16, connect the pcie_sw_done output from ATX PLL to pipe_sw_done input of the Native PHY IP.

For Gen3x2, x4, x8, x16, pcie_sw_done output from ATX PLL to pipe_sw_done input of the Native PHY IP.

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