L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

2.6. Unused or Idle Transceiver Channels

Unused or idle transceiver clock network performance can degrade over time under the following conditions:
  • FPGA devices are powered up to normal operating conditions and not configured.
  • Designs that plan to use unused transceiver channels in the future by using dynamic reconfiguration or a new device programming file.
  • Transceiver channels are used in the design but switched to the idle state during operation.

If you do not plan to use the unused transceiver channels in the future, no action is needed. Active transceiver channels and non-transceiver circuits are not impacted. For active transceiver channels, do not assert the rx_analogreset and tx_analogreset signals indefinitely.

To preserve the performance of unused transceiver channels, the Intel® Quartus® Prime software can switch the TX/RX channels on and off at low frequency using an internally-generated clock. To create clock activity on unused channels by way of a Quartus Settings File (.qsf) variable, either:

  • Make a global assignment:
    set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON
  • Use a per-pin assignment:
    set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to pin_name
    For example, if the pin_name is Pin AB44, structure the per-pin assignment with the following syntax.
    set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to AB44

When you perform this procedure, the Intel® Quartus® Prime software instantiates the clock data recovery (CDR) PLL corresponding to each unused receiver channel. The CDR PLL uses OSC_CLK_1 as reference clock and is configured to run at 1 Gbps. To use OSC_CLK_1 as the reference clock, the pin must be assigned a 25, 100, or 125 MHz clock. When you implement these assignments, it causes a power consumption increase per receiver channel.

Use the .qsf variable to preserve the performance of an unused receiver channel under the following conditions:

  • When the transceiver channel is unused
  • When the transceiver channel is configured as a simplex TX channel
  • When the CDR in the receiver channel is configured as a CMU PLL
  • When the receiver pin is configured as a reference clock pin

Use the .qsf variable to preserve the performance of an unused transmitter channel under the following conditions:

  • When the transceiver channel is unused
  • When the transceiver channel is configured as a simplex RX channel

If you do not perform this procedure, a critical warning similar to the following appears:

Critical Warning (19527): There are 95 unused RX channels and 95 unused TX channels in the design.

Info(19528): Add the QSF assignment 'set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to <pin_name>' for each unused channel you want to preserve.

Info(19529): The above QSF assignment preserves the performance of specified channels over time.

To disable this warning, use the following assignment:

set_instance_assignment -name MESSAGE_DISABLE 19527

When you apply the .qsf variable to a transceiver tile, at least one channel in a transceiver tile needs to be instantiated in the design. If all channels in a tile are unused but you plan to activate one or more in the future, instantiate a dummy channel in the tile.

If a transceiver channel in use is switched to an unused or idle state on the fly, implement the follow steps to preserve the performance of the channel during idle state:

  1. If the channel is designed to support multiple configuration profiles, dynamically reconfigure the channel to the lowest speed profile in the design for less power consumption.
  2. If the channel is not designed to support multiple configuration profiles, create a 1 Gbps channel profile in the Native PHY IP. Dynamically reconfigure the channel to this profile.
  3. Use Direct Reconfiguration Flow to turn on internal serial loopback. This step is optional.
    • You can enable internal serial loopback by asserting the rx_seriallpbken control input port.
    • Alternatively, write 1'b1 to the RX Serial Loopback transceiver register. Refer to Optional Reconfiguration Logic PHY- Control & Status.
  4. Make sure the TX PMA data path is toggling by performing one of the following:
    • Turn on the built-in PRBS generator in the TX PMA.
    • Drive the transmitter channel with scrambled or toggling data pattern from FPGA fabric, such as PRBS or clock.
  5. Tristate the TX buffer. This step is optional to prevent data transmission on the link. Assert the tx_pma_elecidle port to turn off the TX buffer output.
    • An alternative method to tristate TX buffer is to set PMA channel DPRIO register 0x120 bit 7 to 1'b1.
  6. If DFE is enabled for the channel, use Direct Reconfiguration Flow to turn on DFE with all taps on. This incurs additional power. Refer to Setting RX PMA Adaptation Modes.

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