L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

2.2.6. Modify Native PHY IP Core SDC

IP SDC is a new feature of the Native PHY IP core.

IP SDC is produced for any clock that reaches the FPGA fabric. In transceiver applications where the tx_clkouts and rx_clkouts (plus some more) are routed to the FPGA fabric, these clocks have SDC constraints on them in the Native PHY IP core.

Did you find the information on this page useful?

Characters remaining:

Feedback Message