L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 1/30/2024
Document Table of Contents

3.11.3. Implementing PLL Cascading

In PLL cascading, the output of the first PLL feeds the input reference clock to the second PLL.

For example, if the input reference clock has a fixed frequency, and the desired data rate was not an integer multiple of the input reference clock, the first PLL can be used to generate the correct reference clock frequency. This output is fed as the input reference clock to the second PLL. The second PLL generates the clock frequency required for the desired data rate.

The transceivers in Intel® Stratix® 10 devices support fPLL to fPLL and ATX PLL to fPLL cascading. The first PLL (cascade source) and second PLL (downstream PLL) have to be in the same 24-channel tile. For OTN and SDI applications, there is a dedicated clock path for cascading ATX PLL to fPLL.

Note: When the fPLL is used as a cascaded fPLL (downstream fPLL), a user recalibration on the fPLL is required. Refer to User Recalibration section for more information.
Figure 170. PLL Cascading

Steps to implement fPLL to fPLL cascading:

  1. Instantiate the fPLL IP core.
  2. Set the following configuration settings for the fPLL IP core in the Parameter Editor:
    • Set the fPLL Mode to Cascade Source.
    • Set the Desired output clock frequency.
  3. Instantiate the fPLL IP core (the second PLL in PLL cascading configuration). Refer to Instantiating the fPLL IP Core for detailed steps.
  4. Configure the second fPLL IP core for the desired data rate and the reference clock frequency. Set reference clock frequency for the second fPLL same as the output frequency of the first fPLL.
  5. Connect the fPLL IP core (cascade source) to fPLL IP core (transceiver PLL) as shown in the above figure. Ensure the following connections:
    • The fPLL has an output port pll_cascade_clk. Connect this port to the second fPLL's pll_refclk0 port.
  6. If the input reference clock is available at device power-up, the first PLL will be calibrated during the power-up calibration. The second PLL needs to be recalibrated. If the input reference clock is not available at device power-up, then re-run the calibration for the first PLL. After the first PLL has been properly calibrated, re-calibrate the second PLL.


  • No special configuration is required for the Native PHY instance.
  • ATX PLL to fPLL cascading mode is added to address the OTN and SDI jitter requirement. In this mode, ATX PLL generates a relatively high and clean reference frequency in fractional mode. The reference is driving the fPLL, which is running in integer mode. Overall cascaded two PLLs, synthesize a needed frequency for a given data rate.
  • You can update the ATX PLL fractional multiply factor value via the reconfiguration interface of the ATX PLL.
  • You may use this configuration to generate clock frequencies that cannot be generated by a single PLL. It is most commonly used for OTN/SDI applications.
  • In ATX PLL to fPLL cascading mode, the pll_locked signal from the ATX PLL does not indicate the ATX PLL lock status. Refer to the downstream fPLL lock signal to indicate if both ATX and fPLL are locked.