L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

2.4.2.10.1. Word Marking Bits

A word marking bit is only required when using double rate transfer mode.

The maximum possible FIFO datapath width in the Intel® Stratix® 10 transceiver is 40 bits wide. To transfer 80 bits of tx_parallel_data or rx_parallel_data (includes data bus and control bits) across the datapath, the parallel data is divided into two data words of 40 bits each. A new marking bit is added to indicate the word boundary in tx_parallel_data or rx_parallel_data, respectively, to mark the lower 40-bit word and the upper 40-bit word.

When channels are configured in double rate transfer mode, you must set the word marking bit of tx_parallel_data to 0 or 1 to indicate the lower or upper 40-bit word on the transmit datapath. On the receive datapath, either the upper or lower word may be received first. You must use the marking bits to realign the data. On the receive datapath, the word marking bits also indicate the lower or the upper word. Usually it is the same as on the transmit datapath (where 0 is the lower word and 1 is the upper word). However, there are some exceptions. For the following configurations, the upper word is received at 0 and the lower word at 1:

  • Enhanced PCS, with interface width of 32 bits
  • PCS Direct, with interface width of 16, 20 and 32 bits

There is a special reset sequence involving the word marking bit that is required when using double rate transfer mode. Refer to the Special TX PCS Reset Release Sequence section for more information.

Refer to the Transceiver PHY PCS-to-Core Interface Reference Port Mapping section for marking bit information.

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