L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

2.3.3. General and Datapath Parameters

You can customize your instance of the Native PHY IP core by specifying parameter values. In the Parameter Editor, the parameters are organized in the following sections for each functional block and feature:
  • General, Common PMA Options, and Datapath Options
  • TX PMA
  • RX PMA
  • Standard PCS
  • Enhanced PCS
  • PCS Direct Datapath
  • PCS-Core Interface
  • Analog PMA Settings (Optional)
  • Dynamic Reconfiguration
  • Generation Options
Table 12.  General, Common PMA Options, and Datapath Options
Parameter Value Description
Message level for rule violations

error

warning

Specifies the messaging level to use for parameter rule violations. Selecting error causes all rule violations to prevent IP generation. Selecting warning displays all rule violations as warnings in the message window and allows IP generation despite the violations. 6
Use fast reset for simulation On/Off When enabled, the IP disables reset staggering in simulation. The reset behavior in simulation is different from the reset behavior in the hardware.
VCCR_GXB and VCCT_GXB supply voltage for the Transceiver

1_0V, 1_1V 7

Selects the VCCR_GXB and VCCT_GXB supply voltage for the transceiver.
Transceiver Link Type sr, lr Selects the type of transceiver link. SR-Short Reach (Chip-to-chip communication), LR-Long Reach (Backplane communication).
Transceiver channel type GX, GXT Specifies the transceiver channel variant.
Transceiver configuration rules

User Selection

Specifies the valid configuration rules for the transceiver.

This parameter specifies the configuration rule against which the Parameter Editor checks your PMA and PCS parameter settings for specific protocols. Depending on the transceiver configuration rule selected, the Parameter Editor validates the parameters and options selected by you and generates error messages or warnings for all invalid settings.

To determine the transceiver configuration rule to be selected for your protocol, refer to Transceiver Protocols using the Intel® Stratix® 10 H-Tile Transceiver Native PHY IP Core table for more details about each transceiver configuration rule.

This parameter is used for rule checking and is not a preset. You need to set all parameters for your protocol implementation.

Note: For a full description of the Transceiver Configuration Rule Parameter Settings, refer to Transceiver Configuration Rule Parameters in this section.
PMA configuration rules

Basic

SATA/SAS

GPON

Specifies the configuration rule for the PMA.

Select Basic for all other protocol modes except for SATA, and GPON.

SATA (Serial ATA) can be used only if the Transceiver configuration rule is set to Basic/Custom (Standard PCS).

Select GPON only if the Transceiver configuration rule is set to Basic (Enhanced PCS).

Transceiver mode

TX/RX Duplex

TX Simplex

RX Simplex

Specifies the operational mode of the transceiver.

  • TX/RX Duplex : Specifies a single channel that supports both transmission and reception.
  • TX Simplex : Specifies a single channel that supports only transmission.
  • RX Simplex : Specifies a single channel that supports only reception.

The default is TX/RX Duplex.

Number of data channels 124

Specifies the number of transceiver channels to be implemented.

The default value is 1.

Data rate < valid transceiver datarate >

Specifies the datarate in megabits per second (Mbps).

Enable datapath and interface reconfiguration On/Off

When you turn this option on, you can preconfigure and dynamically switch between the Standard PCS, Enhanced PCS, and PCS direct datapaths. You cannot enable the simplified data interface option if you intend on using this feature to support channel reconfiguration.

The default value is Off.

Enable simplified data interface On/Off

By default, all 80-bits are ports for the tx_parallel_data and rx_parallel_data buses are exposed. You must understand the mapping of data and control signals within the interface. Refer to the Enhanced PCS TX and RX Control Ports section for details about mapping of data and control signals.

When you turn on this option, the Native PHY IP core presents a simplified data and control interface between the FPGA fabric and transceiver. Only the sub-set of the 80-bits that are active for a particular FPGA fabric width are ports.

You cannot enable simplified data interface when double rate transfer mode is enabled.

The default value is Off.

Enable double rate transfer mode On/Off

When selected, the Native PHY IP core splits the PCS parallel data into two words and each word is transferred to and from the transceiver interface at twice the parallel clock frequency and half the normal width of the fabric core interface.

You cannot enable simplified data interface when double rate transfer mode is enabled.

Enable PIPE EIOS RX Protection On/Off

This feature is available for Gen 2 and Gen 3 PCIe* PIPE interface selectable in Transceiver configuration rules. When selected, the Native PHY IP core improves the fault-tolerance and compatibility. You need to enable Enable dynamic reconfiguration and connect clock and reset.

When selected, Intel® recommends using these commands to enable physical simulation models:
  • In ModelSim: vlog –sv +define+USE_PMA_ORORA_MODELS
  • In VCS: vcs –lcs +define+USE_PMA_ORORA_MODELS
Table 13.  Transceiver Configuration Rule Parameters
Transceiver Configuration Setting Description
Basic/Custom (Standard PCS) Enforces a standard set of rules within the Standard PCS. Select these rules to implement custom protocols requiring blocks within the Standard PCS or protocols not covered by the other configuration rules.
Basic/Custom w /Rate Match (Standard PCS) Enforces a standard set of rules including rules for the Rate Match FIFO within the Standard PCS. Select these rules to implement custom protocols requiring blocks within the Standard PCS or protocols not covered by the other configuration rules.
CPRI (Auto) Enforces rules required by the CPRI protocol. The receiver word aligner mode is set to Auto. In Auto mode, the word aligner is set to deterministic latency.
CPRI (Manual) Enforces rules required by the CPRI protocol. The receiver word aligner mode is set to Manual. In Manual mode, logic in the FPGA fabric controls the word aligner.
GbE Enforces rules that the 1 Gbps Ethernet (1 GbE) protocol requires.
GbE 1588 Enforces rules for the 1 GbE protocol with support for Precision time protocol (PTP) as defined in the IEEE 1588 Standard.
Gen1 PIPE Enforces rules for a Gen1 PCIe PIPE interface that you can connect to a soft MAC and Data Link Layer.
Gen2 PIPE Enforces rules for a Gen2 PCIe PIPE interface that you can connect to a soft MAC and Data Link Layer.
Gen3 PIPE Enforces rules for a Gen3 PCIe PIPE interface that you can connect to a soft MAC and Data Link Layer.
Basic (Enhanced PCS) Enforces a standard set of rules within the Enhanced PCS. Select these rules to implement protocols requiring blocks within the Enhanced PCS or protocols not covered by the other configuration rules.
Interlaken Enforces rules required by the Interlaken protocol.
10GBASE-R Enforces rules required by the 10GBASE-R protocol.
10GBASE-R 1588 Enforces rules required by the 10GBASE-R protocol with 1588 enabled. This setting can also be used to implement CPRI protocol version 6.0 and later.
10GBASE-R w/KR FEC Enforces rules required by the 10GBASE-R protocol with KR FEC block enabled.
40GBASE-R w/KR FEC Enforces rules required by the 40GBASE-R protocol with the KR FEC block enabled.
Basic w/KR FEC Enforces a standard set of rules required by the Enhanced PCS when you enable the KR FEC block. Select this rule to implement custom protocols requiring blocks within the Enhanced PCS or protocols not covered by the other configuration rules.
PCS Direct Enforces rules required by the PCS Direct mode. In this configuration the data flows through the PCS channel, but all the internal PCS blocks are bypassed. If required, the PCS functionality can be implemented in the FPGA fabric.
6 Although you can generate the PHY with warnings, you may not be able to compile the PHY in Intel® Quartus® Prime Pro Edition.
7 Refer to the Intel® Stratix® 10Device Datasheet for details about the minimum, typical, and maximum supply voltage specifications.

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