L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 1/30/2024
Public
Document Table of Contents

4.5.1. Parameterizing Transceiver PHY Reset Controller Intel® Stratix® 10 FPGA IP

This section lists steps to configure the Transceiver PHY Reset Controller Intel® Stratix® 10 FPGA IP in the IP Catalog. You can customize the following Transceiver PHY Reset Controller Intel® Stratix® 10 FPGA IP parameters for different modes of operation.

To parameterize and instantiate the Transceiver PHY Reset Controller Intel® Stratix® 10 FPGA IP:

  1. Make sure the correct Device Family is selected under Assignments > Device.
  2. Click Tools > IP Catalog > , then Installed IP > Library > Interface Protocols > Transceiver PHY > Transceiver PHY Reset Controller Intel® Stratix® 10 FPGA IP.
  3. Select the options required for your design. For a description of these options, refer to the Transceiver PHY Reset Controller Intel Stratix 10 FPGA IP Parameters.
  4. Click Finish. The wizard generates files representing your parameterized IP variation for synthesis and simulation.