L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

2.5.4.2. Transceiver Channel Datapath and Clocking for CPRI

Figure 132. Transceiver Channel Datapath and Clocking for CPRI using the Standard PCS
Note: The PRBS generator, verifier, and rate match FIFO blocks are not available in the CPRI implementation.
Table 118.  Clock Frequencies for Various CPRI Data Rates using the Standard PCSThese clock frequencies are based on a -1 transceiver speed grade device with 8B/10B encoding and the Standard PCS. Some configurations may not be available depending on the speed grade of your device..
Protocol, Data Rate (Mbps) PMA Interface PLD Interface Byte Serializer Double Rate Transfer Data Transfer Mode

TX Core FIFO tx_coreclkin

AND

RX Core FIFO rx_coreclkin (MHz)

CPRI 1.4, 614.4 10 8/10 OFF Half Rate 61.44
16/20 x2 ON Double Rate 61.44
OFF Full Rate 30.72
20 16/20 ON Double Rate 61.44
OFF Half Rate 30.72
32/40 x2 ON Double Rate 30.72
OFF Full Rate 15.36
CPRI 1.4, 1228.8 10 8/10 OFF Half Rate 122.88
16/20 x2 ON Double Rate 122.88
OFF Full Rate 61.44
20 16/20 ON Double Rate 122.88
OFF Half Rate 61.44
32/40 x2 ON Double Rate 61.44
OFF Full Rate 30.72
CPRI 1.4, 2457.6 10 8/10 OFF Half Rate 245.76
16/20 x2 ON Double Rate 245.76
OFF Full Rate 122.88
20 16/20 ON Double Rate 245.76
OFF Half Rate 122.88
32/40 x2 ON Double Rate 122.88
OFF Full Rate 61.44
CPRI 3.0, 3072 10 8/10 OFF Half Rate 307.2
16/20 x2 ON Double Rate 307.2
OFF Full Rate 153.6
20 16/20 ON Double Rate 307.0
OFF Half Rate 153.6
32/40 x2 ON Double Rate 153.6
OFF Full Rate 76.8
CPRI 4.1, 4915.2 10 8/10 OFF Half Rate N/A 41
16/20 x2 ON Double Rate N/A 41
OFF Full Rate N/A 41
20 16/20 ON Double Rate 491.52
OFF Half Rate 245.76
32/40 x2 ON Double Rate 245.76
OFF Full Rate 122.88
CPRI 4.1, 6144 10 8/10 OFF Half Rate N/A 41
16/20 x2 ON Double Rate N/A 41
OFF Full Rate N/A 41
20 16/20 ON Double Rate 614.4
OFF Half Rate 307.2
32/40 x2 ON Double Rate 307.2
OFF Full Rate 153.6
CPRI 4.2, 9830.4 10 8/10 OFF Half Rate N/A 41
16/20 x2 ON Double Rate N/A 41
OFF Full Rate N/A 41
20 16/20 ON Double Rate N/A 41
OFF Half Rate 491.52
32/40 x2 ON Double Rate 491.52
OFF Full Rate 245.76
Figure 133. Transceiver Channel Datapath and Clocking for CPRI using the Enhanced PCS
Table 119.  Clock Frequencies for Various CPRI Data Rates using the Enhanced PCSThese clock frequencies are based on a -1 transceiver speed grade device with 64B/66B encoding and the Enhanced PCS. Some of these configurations are not available depending on the speed grade of your device.
Protocol,Datarate (Mbps) PMA Interface FPGA Fabric to/from PCS-Core Interface Double Rate Transfer Data Transfer Mode

TX Core FIFO tx_coreclkin

OR

RX Core FIFO rx_coreclkin (MHz)

CPRI 6.1, 8110.08 40 66 OFF Full Rate 202.752
ON Double Rate 405.504
CPRI 6.0, 10137.6 40 66 OFF Full Rate 253.44
ON Double Rate 506.88
CPRI 6.1, 12165.12 40 66 OFF Full Rate 304.128
ON Double Rate 608.256
Table 120.  Interface Width Options for 10.1376 Gbps and 12.16512 Gbps Data Rates
Serial Data Rate (Mbps) Interface Width
FPGA fabric - Enhanced PCS (bits) Enhanced PCS - PMA (bits)
10137.6 66 32, 40, 64
12165.12 66 40, 64
41 This is not a possible implementation for a -1 speed grade device.

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