126.96.36.199.1. TX Data Bitslip
In the Enhanced PCS, the bit slip feature in the TX gearbox allows you to slip the transmitter bits before they are sent to the serializer.
The value specified on the TX bit slip bus indicates the number of bit slips. The minimum slip is one UI. The maximum number of bits slipped is equal to the FPGA fabric-to-transceiver interface width minus 1. For example, if the FPGA fabric-to transceiver interface width is 64 bits; the bit slip logic can slip a maximum of 63 bits. Each channel has six bits to determine the number of bits to slip. The TX bit slip bus is a level-sensitive port, so the TX serial data is bit slipped statically by TX bit slip port assignments. Each TX channel has its own TX bit slip assignment and the bit slip amount is relative to the other TX channels. You can improve lane-to-lane skew by assigning TX bit slip ports with proper values. The following figure shows the effect of slipping tx_serial_data by one UI to reduce the skew with tx_serial_data. After the bit slip tx_serial_data and tx_serial_data are aligned.
Refer to the TX Gearbox, TX Bitslip and Polarity Inversion section for more information.
When using the Standard PCS, select the Enable TX bitslip and Enable tx_std_bitslipboundarysel port options to use the TX bitslip feature. This adds the tx_std_bitslipboundarysel input port. The TX PCS automatically slips the number of bits specified by tx_std_bitslipboundarysel. There is no port for TX bit slip. If there is more than one channel in the design, x_std_bitslipboundarysel ports are multiplied by the number of channels. You can verify this feature by monitoring the tx_parallel_data port. Enabling the TX bit slip feature is optional.
tx_parallel_data = 8'hbc. tx_std_bitslipboundarysel = 5'b00001 (bit slip by 1 bit).
tx_parallel_data = 10'h3bc. tx_std_bitslipboundarysel = 5'b00011 (bit slip by 3 bits).
tx_parallel_data = 16'hfcbc. tx_std_bitslipboundarysel =5'b00011 (bit slip by 3 bits).
Refer to the TX Bit Slip section for more information