L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

2.4.4.4.1. On-die Instrumentation Overview

The ODI block works by sweeping the horizontal phase values and vertical voltage values and comparing it against the recovered data to capture the eye opening.

The clock data recovery (CDR) unit’s recovered clock is fed through a phase interpolator, which has 128 possible resolutions covering 2 UI. The phase interpolator’s output clocks the ODI data sampler, which compares the receiver input after the RX equalizer’s value with a voltage reference (64 levels for the top half of the eye and 64 levels for the bottom half of the eye). You can access both the phase interpolator and the ODI data sampler’s voltage reference from the FPGA core through the Native PHY IP core’s Avalon® memory-mapped interface. The output of the ODI’s data sampler is compared with the CDR data sampler through a serial bit checker. When the DFE is enabled, you must configure the serial bit checker to check for four different data patterns because the DFE is speculative. The number of bits tested and the number of error bits caught in the serial bit checker is summed in an accumulator. You can access the accumulator’s output to the FPGA core through the Native PHY IP core’s Avalon® memory-mapped interface. The ODI implementation allows you to measure the bit error rate (BER) of live traffic.

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