L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

2.5.1.14. Timing Closure Recommendations

When using the Native PHY IP core to implement PCIe PIPE, observe these timing closure recommendations.

When using PCIe PIPE in bonded configurations (x2, x4, x8, x16), use the pclk (tx_clkout from the TX bonding master channel) to drive all the tx_coreclkin and rx_coreclkin clock inputs. The Timing Analyzer may report timing violations if you use the tx_clkout output of each channel to drive the corresponding tx_coreclkin and rx_coreclkin inputs of the Native PHY IP core.

Note: The Native PHY IP core creates all the timing constraints between each channel and the PCIe speed (Gen1, Gen2, Gen3, as applicable) for the TX and RX output clock pins (tx_clkout, tx_clkout_2, rx_clkout, rx_clkout_2). Refer to the sdc file generated by the Native PHY IP core in <Project folder / Native PHY IP Instance / altera_xcvr_native_s10_htile_version / synth / pipe_gen3_x8_native_ip_altera_xcvr_native_s10_htile_inst.sdc> for details about how the Native PHY IP core clocks are constrained.

Design Example

Select Generate Example Design to create a PCIe PIPE design example that you can simulate and download to hardware. The Intel® Quartus® Prime project, settings files, and the IP files are available in the following location in the project folder:

<Project Folder> / <…example_design>

Refer to the "Design Example” table in the Native PHY IP Core Parameter Settings for PIPE section for more details on the parameters to choose for PCIe PIPE configurations.

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