126.96.36.199. Timing Closure Recommendations
When using the Native PHY IP core to implement PCIe PIPE, observe these timing closure recommendations.
When using PCIe PIPE in bonded configurations (x2, x4, x8, x16), use the pclk (tx_clkout from the TX bonding master channel) to drive all the tx_coreclkin and rx_coreclkin clock inputs. The Timing Analyzer may report timing violations if you use the tx_clkout output of each channel to drive the corresponding tx_coreclkin and rx_coreclkin inputs of the Native PHY IP core.
Select Generate Example Design to create a PCIe PIPE design example that you can simulate and download to hardware. The Intel® Quartus® Prime project, settings files, and the IP files are available in the following location in the project folder:
<Project Folder> / <…example_design>
Refer to the "Design Example” table in the Native PHY IP Core Parameter Settings for PIPE section for more details on the parameters to choose for PCIe PIPE configurations.
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