2.3.4. PMA Parameters
- TX Bonding Options
- TX PLL Options
- TX PMA Optional Ports
- RX CDR Options
- RX PMA Optional Ports
|TX channel bonding mode||
PMA only bonding
PMA and PCS bonding
Selects the bonding mode to be used for the channels specified. Bonded channels use a single TX PLL to generate a clock that drives multiple channels, reducing channel-to-channel skew. The following options are available:
Not bonded: In a non-bonded configuration, only the high speed serial clock is expected to be connected from the TX PLL to the Native PHY IP core. The low speed parallel clock is generated by the local clock generation block (CGB) present in the transceiver channel. For non-bonded configurations, because the channels are not related to each other and the feedback path is local to the PLL, the skew between channels cannot be calculated.
PMA only bonding: In PMA bonding, the high speed serial clock is routed from the transmitter PLL to the master CGB. The master CGB generates the high speed and low parallel clocks and the local CGB for each channel is bypassed. Refer to the Channel Bonding section for more details.
PMA and PCS bonding : In a PMA and PCS bonded configuration, the local CGB in each channel is bypassed and the parallel clocks generated by the master CGB are used to clock the network. The master CGB generates both the high and low speed clocks. The master channel generates the PCS control signals and distributes to other channels through a control plane block.
The default value is Not bonded.Refer to Channel Bonding section in PLLs and Clock Networks chapter for more details.
|PCS TX channel bonding master||Auto, 0 to <number of channels> -1||
This feature is only available if PMA and PCS bonding mode has been enabled. Specifies the master PCS channel for PCS bonded configurations. Each Native PHY IP core instance configured with bonding must specify a bonding master. If you select Auto, the Native PHY IP core automatically selects a recommended channel.
The default value is Auto. Refer to the PLLs and Clock Networks chapter for more information about the TX channel bonding master.
|Actual PCS TX channel bonding master||0 to <number of channels> -1||
This parameter is automatically populated based on your selection for the PCS TX channel bonding master parameter. Indicates the selected master PCS channel for PCS bonded configurations.
|PCS reset sequence||
|Selects whether PCS tx/rx_digitalreset is asserted and deasserted independently or simultaneously. Selecting independent staggers the assertion and deassertion of the PCS reset of each transceiver channel one after the other. The independent setting is recommended for PCS non-bonded configurations. Selecting simultaneous, simultaneously asserts and deasserts all the PCS resets of each transceiver channel. Simultaneous setting is required for the following operations:
|TX local clock division factor||
1, 2, 4, 8
Specifies the value of the divider available in the transceiver channels to divide the TX PLL output clock to generate the correct frequencies for the parallel and serial clocks.
|Number of TX PLL clock inputs per channel||
1, 2, 3 , 4
Specifies the number of TX PLL clock inputs per channel. Use this parameter when you plan to dynamically switch between TX PLL clock sources. Up to four input sources are possible.
|Initial TX PLL clock input selection||
0 to <number of TX PLL clock inputs> -1
|Specifies the initially selected TX PLL clock input. This parameter is necessary when you plan to switch between multiple TX PLL clock inputs.|
|Enable tx_pma_iqtxrx_clkout port||On/Off||Enables the optional tx_pma_iqtxrx_clkout output clock. This clock can be used to cascade the TX PMA output clock to the input of a PLL.|
|Enable tx_pma_elecidle port||On/Off||Enables the tx_pma_elecidle port. When you assert this port, the transmitter is forced into an electrical idle condition. This port has no effect when the transceiver is configured for PCI Express.|
|Number of CDR reference clocks||1 - 5||
Specifies the number of CDR reference clocks. Up to 5 sources are possible.
The default value is 1.
|Selected CDR reference clock||0 to <number of CDR reference clocks> -1||
Specifies the initial CDR reference clock. This parameter determines the available CDR references used.
The default value is 0.
|Selected CDR reference clock frequency||< datarate dependent >||
Specifies the CDR reference clock frequency. This value depends on the datarate specified.
You should choose a lane datarate that results in a standard board oscillator reference clock frequency to drive the CDR reference clock and meet jitter requirements. Choosing a lane datarate that deviates from standard reference clock frequencies may result in custom board oscillator clock frequencies, which may be prohibitively expensive or unavailable.
|PPM detector threshold||
Specifies the PPM threshold for the CDR. If the PPM between the incoming serial data and the CDR reference clock exceeds this threshold value, the CDR declares lose of lock.
The default value is 1000.
|Enable rx_pma_iqtxrx_clkout port||On/Off||Enables the optional rx_pma_iqtxrx_clkout output clock. This clock can be used to cascade the RX PMA output clock to the input of a PLL.|
|Enable rx_pma_clkslip port||On/Off|| Enables the optional rx_pma_clkslip control input port.
When asserted, causes the deserializer to either skip one serial bit or pauses the serial clock for one cycle to achieve word alignment.
|Enable rx_is_lockedtodata port||On/Off||Enables the optional rx_is_lockedtodata status output port. This signal indicates that the RX CDR is currently in lock to data mode or is attempting to lock to the incoming data stream. This is an asynchronous output signal.|
|Enable rx_is_lockedtoref port||On/Off||Enables the optional rx_is_lockedtoref status output port. This signal indicates that the RX CDR is currently locked to the CDR reference clock. This is an asynchronous output signal.|
|Enable rx_set_lockedtodata port and rx_set_lockedtoref ports||On/Off||Enables the optional rx_set_lockedtodata and rx_set_lockedtoref control input ports. You can use these control ports to manually control the lock mode of the RX CDR. These are asynchronous input signals.|
|Enable PRBS (Pseudo Random Bit Sequence) verifier control and status ports||On/Off||Enables the optional rx_prbs_err, rx_prbs_clr, and rx_prbs_done control ports. These ports control and collect status from the internal PRBS verifier.|
|Enable rx_seriallpbken port||On/Off||Enables the optional rx_seriallpbken control input port. The assertion of this signal enables the TX to RX serial loopback path within the transceiver. This is an asynchronous input signal.|
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