L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

2.3.16.3. PCS-Core Interface Ports: PCS-Direct

Figure 33. PCS-Core Interface Ports: PCS-Direct
Note: In the following table, the tx_parallel_data and rx_parallel_data mappings shown are for a single channel. To determine the mappings for multi-channel designs, the user must scale the single channel mappings with the appropriate channel multipliers. For example, data[31:0] maps to tx_parallel_data[31:0] and rx_parallel_data[31:0] for single channel designs. For multi-channel designs, data[31:0] for every channel would map to tx_parallel_data[<n-1>80+31:<n-1>80] and rx_parallel_data[<n-1>80+31:<n-1>80], where <n> is the channel number.
Table 81.  Simplified Data Interface=Disabled, Double-Rate Transfer=Disabled
TX Port Function TX Port RX Port Function RX Port
Configuration-28, PMA Width-8, FPGA Fabric width-8
data[7:0] tx_parallel_data[7:0] data[7:0] rx_parallel_data[7:0]
tx_fifo_wr_en tx_parallel_data[79] rx_data_valid rx_parallel_data[79]
Configuration-29, PMA Width-10, FPGA Fabric width-10
data[9:0] tx_parallel_data[9:0] data[9:0] rx_parallel_data[9:0]
tx_fifo_wr_en tx_parallel_data[79] rx_data_valid rx_parallel_data[79]
Configuration-30, PMA Width-16, FPGA Fabric width-16
data[15:0] tx_parallel_data[15:0] data[15:0] rx_parallel_data[15:0]
tx_fifo_wr_en tx_parallel_data[79] rx_data_valid rx_parallel_data[79]
Configuration-31, PMA Width-20, FPGA Fabric width-20
data[19:0] tx_parallel_data[19:0] data[19:0] rx_parallel_data[19:0]
tx_fifo_wr_en tx_parallel_data[79] rx_data_valid rx_parallel_data[79]
Configuration-32, PMA Width-32, FPGA Fabric width-32
data[31:0] tx_parallel_data[31:0] data[31:0] rx_parallel_data[31:0]
tx_fifo_wr_en tx_parallel_data[79] rx_prbs_err rx_parallel_data[35]
    rx_prbs_done rx_parallel_data[36]
rx_data_valid rx_parallel_data[79]
Configuration-33, PMA Width-40, FPGA Fabric width-40
data[39:0] tx_parallel_data[39:0] data[39:0] rx_parallel_data[39:0]
tx_fifo_wr_en tx_parallel_data[79] rx_data_valid rx_parallel_data[79]
Configuration-34, PMA Width-64, FPGA Fabric width-64
data[31:0] tx_parallel_data[31:0] data[31:0] rx_parallel_data[31:0]
data[63:32] tx_parallel_data[71:40] data[63:32] rx_parallel_data[71:40]
tx_fifo_wr_en tx_parallel_data[79] rx_data_valid rx_parallel_data[79]
Note: In the following table, the tx_parallel_data and rx_parallel_data mappings shown are for a single channel. To determine the mappings for multi-channel designs, the user must scale the single channel mappings with the appropriate channel multipliers. For example, data[31:0] maps to tx_parallel_data[31:0] and rx_parallel_data[31:0] for single channel designs. For multi-channel designs, data[31:0] for every channel would map to tx_parallel_data[<n-1>80+31:<n-1>80] and rx_parallel_data[<n-1>80+31:<n-1>80], where <n> is the channel number.
Table 82.  Simplified Data Interface=Disabled, Double-Rate Transfer=Enabled
TX Port Function TX Port RX Port Function RX Port
Configuration-35, PMA Width-16, FPGA Fabric width-8
data[7:0] tx_parallel_data[7:0] (lower word) data[7:0] rx_parallel_data[7:0] (lower word)
data[15:8] tx_parallel_data[7:0] (upper word) data[15:8] rx_parallel_data[7:0] (upper word)
tx_word_marking_bit=0 tx_parallel_data[19] (lower word) rx_word_marking_bit=0 rx_parallel_data[39] (upper word)
tx_word_marking_bit=1 tx_parallel_data[19] (upper word) rx_word_marking_bit=1 rx_parallel_data[39] (lower word)
tx_fifo_wr_en tx_parallel_data[79] (lower and upper word) rx_data_valid rx_parallel_data[79]
Configuration-36, PMA Width-20, FPGA Fabric width-10
data[9:0] tx_parallel_data[9:0] (lower word) data[9:0] rx_parallel_data[9:0] (lower word)
data[19:10] tx_parallel_data[9:0] (upper word) data[19:10] rx_parallel_data[9:0] (upper word)
tx_word_marking_bit=0 tx_parallel_data[19] (lower word) rx_word_marking_bit=0 rx_parallel_data[39] (upper word)
tx_word_marking_bit=1 tx_parallel_data[19] (upper word) rx_word_marking_bit=1 rx_parallel_data[39] (lower word)
tx_fifo_wr_en tx_parallel_data[79] (lower and upper word) rx_data_valid rx_parallel_data[79]
Configuration-37, PMA Width-32, FPGA Fabric width-16
data[15:0] tx_parallel_data[15:0] (lower word) data[15:0] rx_parallel_data[15:0] (lower word)
data[31:16] tx_parallel_data[15:0] (upper word) data[31:16] rx_parallel_data[15:0] (upper word)
tx_word_marking_bit=0 tx_parallel_data[19] (lower word) rx_word_marking_bit=0 rx_parallel_data[39] (upper word)
tx_word_marking_bit=1 tx_parallel_data[19] (upper word) rx_word_marking_bit=1 rx_parallel_data[39] (lower word)
tx_fifo_wr_en tx_parallel_data[79] (lower and upper word) rx_data_valid rx_parallel_data[79]
Configuration-38, PMA Width-40, FPGA Fabric width-20
data[19:0] tx_parallel_data[19:0] (lower word) data[19:0] rx_parallel_data[19:0] (lower word)
data[39:20] tx_parallel_data[19:0] (upper word) data[39:20] rx_parallel_data[19:0] (upper word)
tx_word_marking_bit=0 tx_parallel_data[39] (lower word) rx_word_marking_bit=0 rx_parallel_data[39] (lower word)
tx_word_marking_bit=1 tx_parallel_data[39] (upper word) rx_word_marking_bit=1 rx_parallel_data[39] (upper word)
tx_fifo_wr_en tx_parallel_data[79] (lower and upper word) rx_data_valid rx_parallel_data[79] (lower and upper word)
Configuration-39, PMA Width-64, FPGA Fabric width-32
data[31:0] tx_parallel_data[31:0] (lower word) data[31:0] rx_parallel_data[31:0] (lower word)
data[63:32] tx_parallel_data[31:0] (upper word) data[63:32] rx_parallel_data[31:0] (upper word)
tx_word_marking_bit=0 tx_parallel_data[39] (lower word) rx_word_marking_bit=0 rx_parallel_data[39] (lower word)
tx_word_marking_bit=1 tx_parallel_data[39] (upper word) rx_word_marking_bit=1 rx_parallel_data[39] (upper word)
tx_fifo_wr_en tx_parallel_data[79] (lower and upper word) rx_data_valid rx_parallel_data[79] (lower and upper word)

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