L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 10/05/2023
Public
Document Table of Contents

2.4.2.1.1. Word Alignment Using the Standard PCS

To achieve receiver word alignment, use the word aligner of the Standard PCS in one of the following modes:

  • RX data bitslip
  • Manual mode
  • Synchronous State Machine
  • Deterministic Latency Mode
  • Word alignment in GbE Mode

RX Bitslip

To use the RX bitslip, select Enable rx_bitslip port and set the word aligner mode to bitslip. This adds rx_bitslip as an input control port. An active high edge on rx_bitslip slips one bit at a time. When rx_bitslip is toggled, the word aligner slips one bit at a time on every active high edge. Assert the rx_bitslip signal for at least 200 ns to ensure it passes through the slow shift register. You can verify this feature by monitoring rx_parallel_data.

The RX bitslip feature is optional and may or may not be enabled.

Figure 37. RX Bitslip in 8-bit Mode tx_parallel_data = 8'hbc
Figure 38. RX Bitslip in 10-bit Mode tx_parallel_data = 10'h3bc
Figure 39. RX Bitslip in 16-bit Mode tx_parallel_data = 16'hfcbc
Figure 40. RX Bitslip in 20-bit Mode tx_parallel_data = 20'h3fcbc

Refer to the Word Aligner bitslip Mode section for more information.

Word Aligner Manual Mode

Refer to the Intel® Stratix® 10 (L/H-Tile) Word Aligner Bitslip Calculator to calculate the number of slips you require to achieve alignment based on the word alignment pattern and length. To use this mode:

  1. Set the RX word aligner mode to Manual (FPGA Fabric controlled).
  2. Set the RX word aligner pattern length option according to the PCS-PMA interface width.
  3. Enter a hexadecimal value in the RX word aligner pattern (hex) field.

This mode adds rx_patterndetect and rx_syncstatus. You can select the Enable rx_std_wa_patternalign port option to enable rx_std_wa_patternalign.

Note:
  • rx_patterndetect is asserted whenever there is a pattern match.
  • rx_syncstatus is asserted after the word aligner achieves synchronization, 3 clkout cycles after rx_patterndetect goes high.
  • rx_std_wa_patternalign is asserted to re-align and resynchronize.
  • If there is more than one channel in the design, rx_patterndetect, rx_syncstatus and rx_std_wa_patternalign become buses in which each bit corresponds to one channel.

You can verify this feature by monitoring rx_parallel_data.

The following timing diagrams demonstrate how to use the ports and show the relationship between the various control and status signals. In the top waveform, rx_parallel_data is initially misaligned. After asserting the rx_std_wa_patternalign signal, it becomes aligned. The bottom waveform shows the behavior of the rx_syncstatus signal when rx_parallel_data is already aligned.

Figure 41. Manual Mode when the PCS-PMA Interface Width is 8 Bits tx_parallel_data = 8'hBC and the word aligner pattern = 8'hBC

In manual alignment mode, the word alignment operation is manually controlled with the rx_std_wa_patternalign input signal or the rx_enapatternalign register. The word aligner operation is level-sensitive to rx_enapatternalign. The word aligner asserts the rx_syncstatus signal for one parallel clock cycle whenever it re-aligns to the new word boundary.

Note: Only the 10-bit mode is level sensitive. The 8-, 16-, and 20-bit modes are edge sensitive.

Refer to the Word Aligner Manual Mode section for more information.

Word Aligner Synchronous State Machine Mode

To use this mode:

  • Select the Enable TX 8B/10B encoder option.
  • Select the Enable RX 8B/10B decoder option.

The 8B/10B encoder and decoder add the following additional ports:

  • tx_datak
  • rx_datak
  • rx_errdetect
  • rx_disperr
  • rx_runningdisp
  1. Set the RX word aligner mode to synchronous state machine.
  2. Set the RX word aligner pattern length option according to the PCS-PMA interface width.
  3. Enter a hexadecimal value in the RX word aligner pattern (hex) field.

The RX word aligner pattern is the 8B/10B encoded version of the data pattern. You can also specify the number of word alignment patterns (LSB first) to achieve synchronization, the number of invalid data words to lose synchronization, and the number of valid data words to decrement error count. This mode adds two additional ports: rx_patterndetect and rx_syncstatus.

Note:
  • rx_patterndetect is asserted whenever there is a pattern match.
  • rx_syncstatus is asserted after the word aligner achieves synchronization, 3 clkout cycles after rx_patterndetect goes high.
  • If there is more than one channel in the design, tx_datak, rx_datak, rx_errdetect, rx_disperr, rx_runningdisp, rx_patterndetect, and rx_syncstatus become buses in which each bit corresponds to one channel.

You can verify this feature by monitoring rx_parallel_data.

Figure 42. Synchronization State Machine Mode when the PCS-PMA Interface Width is 16 Bits

Refer to the Word Aligner Synchronous State Machine Mode section for more information.

Word Aligner in Deterministic Latency Mode for CPRI

The deterministic latency state machine in the word aligner reduces the known delay variation from the word alignment process. It automatically synchronizes and aligns the word boundary by slipping one half of a serial clock cycle (1UI) in the deserializer. Incoming data to the word aligner is aligned to the boundary of the word alignment pattern (K28.5).
Figure 43.  Deterministic Latency State Machine in the Word Aligner

When using deterministic latency state machine mode, assert rx_std_wa_patternalign to initiate the pattern alignment after the reset sequence is complete. This is an edge-triggered signal in all cases except one: when the word aligner is in manual mode and the PMA width is 10 bits, in which case rx_std_wa_patternalign is level sensitive.

Figure 44. Word Aligner in Deterministic Latency Mode 16 Bits Waveform

Calculating Latency through the Word Aligner

You can use the word aligner in either of the following modes to achieve deterministic latency:
  • Deterministic Latency State Machine (DLSM)
  • Synchronous State Machine (SSM)
  • Manual mode
  • RX Bitslip mode
Table 85.  Word Aligner Latency in DLSM and RX Bitslip Modes
Condition Latency
If rx_std_bitslipboundarysel 19 is EVEN Constant
If rx_std_bitslipboundarysel 19 is ODD Constant + 1 UI
Table 86.  Word Aligner Latency in SSM and Manual Modes
Condition Latency
10-bit PMA Constant (nsec) + (rx_std_bitslipboundarysel) * UI 20 (nsec)
20-bit PMA Constant (nsec) + (19 - rx_std_bitslipboundarysel) * UI20 (psec)

Word Alignment in GbE Mode

The word aligner for the GbE and GbE with IEEE 1588v2 protocols is configured in automatic synchronization state machine mode.

The Intel® Quartus® Prime Pro Edition software automatically configures the synchronization state machine to indicate synchronization when the receiver receives three consecutive synchronization ordered sets. A synchronization ordered set is a /K28.5/ code group followed by an odd number of valid /Dx.y/ code groups. The fastest way for the receiver to achieve synchronization is to receive three continuous {/K28.5/, /Dx.y/} ordered sets.

The Native PHY IP core signals receiver synchronization status on the rx_syncstatus port of each channel. A high on the rx_syncstatus port indicates that the lane is synchronized; a low on the rx_syncstatus port indicates that the lane has fallen out of synchronization. The receiver loses synchronization when it detects three invalid code groups separated by less than three valid code groups or when it is reset.

Table 87.  Synchronization State Machine Parameter Settings for GbE
Synchronization State Machine Parameter Setting
Number of word alignment patterns to achieve sync 3
Number of invalid data words to lose sync 3
Number of valid data words to decrement error count 3

The following figure shows rx_syncstatus high when three consecutive ordered sets are sent through rx_parallel_data.

Figure 45. rx_syncstatus High


19 If you do not account for rx_std_bitslipboundarysel, there will be nondeterminism of 1 UI in these word aligner modes.
20 UI is the inverse of the serial datarate. These constants have different values based on the PHY configuration. Contact MySupport for further details on the expected values. The rx_std_bitslipboundarysel output status port is available to you at the PCS-Core interface.