L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 1/30/2024
Document Table of Contents Implementing x6/x24 Bonding Mode

Figure 168. Connection between Native PHY IP and PLL IP Cores for x6/x24 Bonding Mode
Note: Although the above diagram looks similar to the "Multi-Channel x1/x24 Non-Bonded Example", the clock input ports on the transceiver channels bypass the local CGB in x6/x24 bonding configuration. This internal connection is taken care of when the Native PHY channel bonding mode is set to Bonded.

Steps to implement a x6/x24 bonded configuration

  1. You can instantiate either the ATX PLL or the fPLL for x6/x24 bonded configuration.
    • Refer to Instantiating the ATX PLL IP Core or Instantiating the fPLL IP Core for detailed steps.

    • Only the ATX PLL or fPLL can be used for bonded configurations, because the CMU PLL cannot drive the Master CGB.
  2. Configure the PLL IP core using the IP Parameter Editor. Enable Include Master Clock Generation Block and Enable bonding clock output ports.
  3. Configure the Native PHY IP core using the IP Parameter Editor.
    • Set the Native PHY IP core TX Channel bonding mode to either PMA bonding or PMA/PCS bonding.
      Note: All channels must be contiguously placed when using PMA/PCS bonding. Refer to the "Channel Bonding" section for more details.
    • Set the number of channels required by your design. In this example, the number of channels is set to 10.
  4. Create a top level wrapper to connect the PLL IP core to Native PHY IP core.
    • In this case, the PLL IP core has tx_bonding_clocks output bus with width [5:0].
    • The Native PHY IP core has tx_bonding_clocks input bus with width [5:0] multiplied by the number of transceiver channels (10 in this case). For 10 channels, the bus width is [59:0].
      Note: While connecting tx_bonding_clocks, leave tx_serial_clk open to avoid any Intel® Quartus® Prime Pro Edition software fitter errors.
    • Connect the PLL IP core to the PHY IP core by duplicating the output of the PLL[5:0] for the number of channels. For 10 channels, the Verilog syntax for the input port connection is .tx_bonding_clocks ({10{tx_bonding_clocks_output}}).
Figure 169. x6/x24 Bonding Mode —Internal Channel Connections