L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

3.10. PLL Cascading Clock Network

The PLL cascading clock network spans the entire tile and is used for PLL cascading.

Figure 164. PLL Cascading Clock Network

To support PLL cascading, the following connections are present:

  1. The C counter output of the fPLL drives the cascading clock network.
  2. The cascading clock network drives the reference clock input of all PLLs.

For PLL cascading, connections (1) and (2) are used to connect the output of one PLL to the reference clock input of another PLL.

The transceivers in Intel® Stratix® 10 devices support fPLL to fPLL and ATX PLL to fPLL (via dedicated ATX PLL to fPLL cascade path) cascading.

In x24 bonding configurations, one PLL is used for each bonded group.

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