L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

6.3.1. Configuration Files

The Intel® Stratix® 10 L-Tile/H-Tile Transceiver Native PHY and Transmit PLL IP cores optionally allow you to save the parameters you specify for the IP instances as configuration files. The configuration file stores addresses and data values for that specific IP instance.

The configuration files are generated during IP generation. They are located in the <IP instance name>/reconfig/ subfolder of the IP instance. The configuration data is available in the following formats:

  • SystemVerilog packages: <name>.sv
  • C Header files: <name>.h
  • Memory Initialization File (MIF): <name>.mif

Select one or more of the configuration file formats on the Dynamic Reconfiguration tab of the Transceiver Native PHY or Transmit PLL parameter editor to store the configuration data. All configuration file formats generated for a particular IP instance contain the same address and data values. The contents of the configuration files can be used to reconfigure from one transceiver PLL configuration to another.

Note: The addresses and bit settings of EMIB for a chosen configuration are available in the configuration files generated by the Native PHY IP.

The configuration files generated by Native PHY IP also include the PMA analog settings specified in the Analog PMA settings tab of the Native PHY IP Parameter Editor. The analog settings selected in the Native PHY IP Parameter Editor are used to include these settings and their dependent settings in the selected configuration files.

SystemVerilog Configuration File

    27'h008FF04, 	
// [26:16]-DPRIO address=0x008;
// [15:8]-bit mask=0xFF; 
// [7:7]- hssi_tx_pcs_pma_interface_pldif_datawidth_mode=pldif_data_10bit(1'h0); 
// [6:5]-hssi_tx_pcs_pma_interface_tx_pma_data_sel=ten_g_pcs(2'h0); 
// [4:4]-hssi_tx_pcs_pma_interface_prbs_gen_pat=prbs_gen_dis(1'h0); 
// [3:0]-hssi_tx_pcs_pma_interface_sq_wave_num=sq_wave_default(4'h4);
…

localparam HSSI_TX_PCS_PMA_INTERFACE_PLDIF_DATAWIDTH_MODE_VALUE = "pldif_data_10bit";
localparam HSSI_TX_PCS_PMA_INTERFACE_PLDIF_DATAWIDTH_MODE_ADDR_OFST = 8;
localparam HSSI_TX_PCS_PMA_INTERFACE_PLDIF_DATAWIDTH_MODE_ADDR_FIELD_OFST = 7;
localparam HSSI_TX_PCS_PMA_INTERFACE_PLDIF_DATAWIDTH_MODE_ADDR_FIELD_HIGH = 7;
localparam HSSI_TX_PCS_PMA_INTERFACE_PLDIF_DATAWIDTH_MODE_ADDR_FIELD_SIZE = 1;
localparam HSSI_TX_PCS_PMA_INTERFACE_PLDIF_DATAWIDTH_MODE_ADDR_FIELD_BITMASK = 
	32'h00000080;
localparam HSSI_TX_PCS_PMA_INTERFACE_PLDIF_DATAWIDTH_MODE_ADDR_FIELD_VALMASK = 
	32'h00000000;
localparam HSSI_TX_PCS_PMA_INTERFACE_PLDIF_DATAWIDTH_MODE_ADDR_FIELD_VALUE = 1'h0;
Note: DPRIO refers to Avalon® memory-mapped interface registers.
The SystemVerilog configuration files contain two parts. The first part consists of a data array of 27-bit hexadecimal values. The second part consists of parameter values. For the data array, each 27-bit hexadecimal value is associated with a comment that describes the various bit positions.
Table 156.   Mapping of SystemVerilog Configuration File Line
Bit Position Description
[26:16] The channel or PLL address.
[15:8] The channel or PLL bit mask. The bit mask exposes the bits that are configured in either the Transceiver Native PHY or the transmit PLL IP cores.
[7:0] Feature bit values.

For example, a value of 27'h008FF04 represents an address of 0x008 and a bit mask of 0xFF. The four features that reside at address 0x008 are:

  • hssi_tx_pcs_pma_interface_pldif_datawidth_mode with a value of 1'h0
  • hssi_tx_pcs_pma_interface_tx_pma_data_sel with a value of 2'h0
  • hssi_tx_pcs_pma_interface_prbs_gen_pat with a value of 1'h0
  • hssi_tx_pcs_pma_interface_sq_wave_num with a value of 4'h4

Writing to bit 7 of address 0x008 changes the hssi_tx_pcs_pma_interface_pldif_datawidth_mode feature.

The MIF file and C header file are set up similarly to the SystemVerilog package file. Multiple transceiver features may reside at the same address. Also, a single transceiver feature may span across multiple addresses.

You can generate multiple configurations (up to 8) of the transceiver Native PHY IP Core, PLL IP Core, or both. One configuration defines the base transceiver or PLL configuration and the other configurations define the modified or target configurations. Use the IP Parameter Editor to create base and modified configurations of the Transceiver Native PHY or PLL IP core, according to the following table.

Table 157.  Transceiver Native PHY or PLL IP Parameters (Base and Modified Configurations)
Native PHY or PLL Instance Required Parameter Settings Saved In

Base Configuration

  • Click Interface Protocols > Transceiver PHY > Intel® Stratix® 10 L-Tile/H-Tile Transceiver Native PHY for the Native PHY IP core. Or, select one of the supported transmit PLL IP cores under PLL. Enable all options required for the base configuration, such as data rate, PCS options, and PMA options.
  • Enable all ports to be used by the modified configuration. For example, if the bitslip feature is not required in the base configuration, but required in modified configuration, then you must enable the tx_std_bitslipboundarysel port. Reconfiguring between Standard PCS, Enhanced PCS, and PCS Direct requires that you turn on Enable datapath and interface reconfiguration. The Transceiver configuration rules define the initial mode of the PHY instance.
  • On the Dynamic Reconfiguration tab, turn on Enable dynamic reconfiguration and specify the Configuration Options.

This flow requires that you turn on Configuration file option.

  • <Native PHY Base Instance Name> /reconfig/altera_xcvr_native_s10_reconfig_parameters.sv contains all transceiver register addresses and their bit value for that transceiver configuration.

Or

  • <PLL Base Instance Name> / reconfig/altera_xcvr_<type>_pll_s10_reconfig_parameters.sv contains all PLL register addresses and their bit value for that PLL configuration.

Modified Configuration

  • Click Interface Protocols > Transceiver PHY > Intel® Stratix® 10 L-Tile/H-Tile Transceiver Native PHY. Or, select one of the supported transmit PLL IP cores under PLL. Enable all options required for the modified configuration, such as data rate, PCS options, and PMA options.
  • Enable all ports that are used by the modified configuration. Reconfiguring between Standard PCS, Enhanced PCS, and PCS Direct requires Enable datapath and interface reconfiguration be enabled. The Transceiver configuration rules define the mode of the PHY instance.
  • On the Dynamic Reconfiguration tab, turn on Enable dynamic reconfiguration and specify the same Configuration Options as the base instance.
  • <Native PHY Modified Instance Name> /reconfig/altera_xcvr_native_s10_reconfig_parameters.sv contains all transceiver register addresses and their bit value for that transceiver configuration.

Or

  • <PLL Modified Instance Name> / reconfig/altera_xcvr_<type>_pll_s10_reconfig_parameters.sv contains all PLL register addresses and their bit value for that PLL configuration.
Note: You can generate the base and modified configuration files in the same or different folders. If you use the same folder, each configuration name must be unique.

Intel® recommends following the flow described in the "Steps to Perform Dynamic Reconfiguration" section when performing dynamic reconfiguration of either the Native PHY IP core, transmit PLL IP core, or both.

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