L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

2.3.2. GXT Channels

You can instantiate up to 16 GXT channels per H-tile and up to eight GXT channels per L-Tile using a Intel® Stratix® 10 L-/H-Tile Native PHY IP instance.

Set the following parameters:

  • Set the VCCR_GXB and VCCT_GXB supply voltage for the transceiver parameter to 1_1V.
  • Set the TX channel bonding mode parameter to Not Bonded.
  • Set the datarate parameter between 17400 and 25800 (L-Tile, and 28300 (H-Tile).
  • Set the number of channels between 1 and 16.

Because each ATX PLL's tx_serial_clk_gt can connect up to 2 GXT channels, you must instantiate one to eight ATX PLLs. Be aware of the GXT channel location and connect the appropriate ATX PLL’s tx_serial_clk_gt port to the Native PHY IP Core's tx_serial_clk port.

Refer to Using the ATX PLL for GXT Channels section for more details.

Refer to AN 778: Intel® Stratix® 10 Transceiver Usage for more information about transceiver channel placement guidelines for both L- and H-Tiles.

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