L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 1/30/2024
Document Table of Contents

6.4. Arbitration

In Intel® Stratix® 10 devices, there are two levels of arbitration:

Figure 237. Arbitration in Intel® Stratix® 10 Transmit PLL
Figure 238. Arbitration in Intel® Stratix® 10 Native PHY
  • Reconfiguration interface arbitration with the PreSICE calibration engine

    When you have control over the internal configuration bus, refer to the second level of arbitration: Arbitration between multiple masters within the Native PHY/PLL IPs.

    For more details about arbitration between the reconfiguration interface and PreSICE, refer to the Calibration chapter.

  • Arbitration between multiple masters within the Native PHY/PLL IPs

    Below are the feature blocks that can access the programmable registers:

    • Embedded reconfiguration streamer
    • NPDME
    • User reconfiguration logic connected to the reconfiguration interface

    When the internal configuration bus is not owned by the PreSICE, which feature block has access depends on which of them are enabled.

    These feature blocks arbitrate for control over the programmable space of each transceiver channel/PLL. Each of these feature blocks can request access to the programmable registers of a channel/PLL by performing a read or write operation to that channel/PLL. For any of these feature blocks to be used, you must first have control over the internal configuration bus. You must ensure that these feature blocks have completed all the read/write operations before you return the bus access to PreSICE.

    The embedded reconfiguration streamer has the highest priority, followed by the reconfiguration interface, followed by the NPDME. When two feature blocks are trying to access the same transceiver channel on the same clock cycle, the feature block with the highest priority is given access. The only exception is when a lower-priority feature block is in the middle of a read/write operation and a higher-priority feature block tries to access the same channel/PLL. In this case, the higher-priority feature block must wait until the lower-priority feature block finishes the read/write operation.

    When you enable NPDME in your design, you must
    • connect an Avalon® memory-mapped interface master to the reconfiguration interface
    • OR connect the reconfig_clock,reconfig_reset signals and ground the reconfig_write, reconfig_read, reconfig_address and reconfig_writedata signals of the reconfiguration interface. If the reconfiguration interface signals are not connected appropriately, there is no clock or reset for the NPDME, and the NPDME does not function as expected.