188.8.131.52. Implementing Single Channel x1 Non-Bonded Configuration
For a single channel design, a PLL is used to provide the clock to a transceiver channel.
Steps to implement a Single-Channel x1 Non-Bonded Configuration
- Choose the PLL IP core (ATX PLL, fPLL, or CMU PLL) you want to instantiate in your design and instantiate the PLL IP core.
- Refer to Instantiating the ATX PLL IP Core, or Instantiating the fPLL IP Core, or Instantiating the CMU PLL IP Core for detailed steps.
- Configure the PLL IP core using the IP Parameter Editor
- For the ATX PLL IP core or the fPLL IP core do not include the Master CGB.
- For the CMU PLL IP core, specify the reference clock and the data rate. No special configuration rule is required.
- Configure the Native PHY IP core using the IP Parameter Editor
- Set the Native PHY IP core TX Channel bonding mode to Non-Bonded.
- Set the number of channels as per your design requirement. In this example, the number of channels is set to 1.
- Create a top level wrapper to connect the PLL IP core to the Native PHY IP core.
- The tx_serial_clk output port of the PLL IP core represents the high speed serial clock.
- The Native PHY IP core has 1 (for this example) tx_serial_clk input ports.
- As shown in the figure above, connect the tx_serial_clk input to the transceiver PLL instance.
Did you find the information on this page useful?