L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

3.11.1.1. Implementing Single Channel x1 Non-Bonded Configuration

In x1 non-bonded configuration, the PLL source is local to the transceiver bank and the x1 clock network is used to distribute the clock from the PLL to the transmitter channel.

For a single channel design, a PLL is used to provide the clock to a transceiver channel.

Figure 165. PHY IP Core and PLL IP Core Connection for Single Channel x1 Non-Bonded Configuration Example

Steps to implement a Single-Channel x1 Non-Bonded Configuration

  1. Choose the PLL IP core (ATX PLL, fPLL, or CMU PLL) you want to instantiate in your design and instantiate the PLL IP core.
    • Refer to Instantiating the ATX PLL IP Core, or Instantiating the fPLL IP Core, or Instantiating the CMU PLL IP Core for detailed steps.
  2. Configure the PLL IP core using the IP Parameter Editor
    • For the ATX PLL IP core or the fPLL IP core do not include the Master CGB.
    • For the CMU PLL IP core, specify the reference clock and the data rate. No special configuration rule is required.
  3. Configure the Native PHY IP core using the IP Parameter Editor
    • Set the Native PHY IP core TX Channel bonding mode to Non-Bonded.
    • Set the number of channels as per your design requirement. In this example, the number of channels is set to 1.
  4. Create a top level wrapper to connect the PLL IP core to the Native PHY IP core.
    • The tx_serial_clk output port of the PLL IP core represents the high speed serial clock.
    • The Native PHY IP core has 1 (for this example) tx_serial_clk input ports.
    • As shown in the figure above, connect the tx_serial_clk input to the transceiver PLL instance.

Did you find the information on this page useful?

Characters remaining:

Feedback Message