L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

2.3.14.1. Enhanced PCS TX and RX Control Ports

This section describes the tx_control and rx_control bit encodings for different protocol configurations.

When Enable simplified data interface is ON, all of the unused ports shown in the tables below, appear as a separate port. For example: It appears as unused_tx_control/ unused_rx_control port.

Enhanced PCS TX Control Port Bit Encodings

Note: When using double rate transfer, refer to the Transceiver PHY PCS-to-Core Interface Reference Port Mapping section.
Table 65.  Bit Encodings for Interlaken
Name Bit Functionality Description
tx_control [1:0] Synchronous header The value 2'b01 indicates a data word. The value 2'b10 indicates a control word.
[2] Inversion control A logic low indicates that the built-in disparity generator block in the Enhanced PCS maintains the Interlaken running disparity.
[7:3] Unused  
[8] Insert synchronous header error or CRC32 You can use this bit to insert synchronous header error or CRC32 errors. The functionality is similar to tx_err_ins. Refer to tx_err_ins signal description in Interlaken Frame Generator, Synchronizer and CRC32 table for more details.
Table 66.  Bit Encodings for 10GBASE-R , 10GBASE-R 1588, 10GBASE-R with KR FEC
Name Bit Functionality
tx_control [0] XGMII control signal for parallel_data[7:0]
[1] XGMII control signal for parallel_data[15:8]
[2] XGMII control signal for parallel_data[23:16]
[3] XGMII control signal for parallel_data[31:24]
[4] XGMII control signal for parallel_data[39:32]
[5] XGMII control signal for parallel_data[47:40]
[6] XGMII control signal for parallel_data[55:48]
[7] XGMII control signal for parallel_data[63:56]
[8] Unused
Table 67.  Bit Encodings for Basic (Enhanced PCS) with 66-bit word, Basic with KR FEC, 40GBASE-R with KR FECFor Basic (Enhanced PCS) with 66-bit word, Basic with KR FEC, 40GBASE-R with KR FEC, the total word length is 66-bit with 64-bit data and 2-bit synchronous header.
Name Bit Functionality Description
tx_control [1:0] Synchronous header The value 2'b01 indicates a data word. The value 2'b10 indicates a control word.
[8:2] Unused  
Table 68.  Bit Encodings for Basic (Enhanced PCS) with 67-bit wordIn this case, the total word length is 67-bit with 64-bit data and 2-bit synchronous header and inversion bit for disparity control.
Name Bit Functionality Description
tx_control [1:0] Synchronous header The value 2'b01 indicates a data word. The value 2'b10 indicates a control word.
[2] Inversion control A logic low indicates that built-in disparity generator block in the Enhanced PCS maintains the running disparity.

Enhanced PCS RX Control Port Bit Encodings

Table 69.  Bit Encodings for Interlaken
Name Bit Functionality Description
rx_control [1:0] Synchronous header The value 2'b01 indicates a data word. The value 2'b10 indicates a control word.
[2] Inversion control A logic low indicates that the built-in disparity generator block in the Enhanced PCS maintains the Interlaken running disparity. In the current implementation, this bit is always tied logic low (1'b0).
[3] Payload word location A logic high (1'b1) indicates the payload word location in a metaframe.
[4] Synchronization word location A logic high (1'b1) indicates the synchronization word location in a metaframe.
[5] Scrambler state word location A logic high (1'b1) indicates the scrambler word location in a metaframe.
[6] SKIP word location A logic high (1'b1) indicates the SKIP word location in a metaframe.
[7] Diagnostic word location A logic high (1'b1) indicates the diagnostic word location in a metaframe.
[8] Synchronization header error, metaframe error, or CRC32 error status A logic high (1'b1) indicates synchronization header error, metaframe error, or CRC32 error status.
[9] Block lock and frame lock status A logic high (1'b1) indicates that block lock and frame lock have been achieved.
Table 70.  Bit Encodings for 10GBASE-R , 10GBASE-R 1588, 10GBASE-R with KR FEC
Name Bit Functionality
rx_control [0] XGMII control signal for parallel_data[7:0]
[1] XGMII control signal for parallel_data[15:8]
[2] XGMII control signal for parallel_data[23:16]
[3] XGMII control signal for parallel_data[31:24]
[4] XGMII control signal for parallel_data[39:32]
[5] XGMII control signal for parallel_data[47:40]
[6] XGMII control signal for parallel_data[55:48]
[7] XGMII control signal for parallel_data[63:56]
[9:8] Unused
Table 71.  Bit Encodings for Basic (Enhanced PCS) with 66-bit word, Basic with KR FEC, 40GBASE-R with KR FECFor Basic (Enhanced PCS) with 66-bit word, Basic with KR FEC, 40GBASE-R with KR FEC, the total word length is 66-bit with 64-bit data and 2-bit synchronous header.
Name Bit Functionality Description
rx_control [1:0] Synchronous header The value 2'b01 indicates a data word. The value 2'b10 indicates a control word.
[7:2] Unused  
[9:8] Unused  
Table 72.  Bit Encodings for Basic (Enhanced PCS) with 67-bit wordIn this case, the total word length is 67-bit with 64-bit data and 2-bit synchronous header and inversion bit for disparity control.
Name Bit Functionality Description
rx_control [1:0] Synchronous header The value 2'b01 indicates a data word. The value 2'b10 indicates a control word.
[2] Inversion control A logic low indicates that built-in disparity generator block in the Enhanced PCS maintains the running disparity.

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