L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

6.13.2.2. Control and Status Registers

Control and status registers are optional registers that memory-map the status outputs from and control inputs to the Native PHY and PLL.

Refer to Logical View of the L-Tile/H-Tile Transceiver Registers for details on Control and Status registers.

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