184.108.40.206.6. Byte Serializer Effects on Data Propagation at the RX Side
In either duplex mode (RX and TX adjacent) or simplex mode, where RX is at the far end compared to TX, the two channels initialize asynchronously. The FPGA core logic can solve this for duplex, but adds more RTL and latency. Additionally, signal integrity/power integrity (SI/PI), power delivery network (PDN), and thermal issues contribute to misalignment.
In scenario (A), the byte serializer is set to the x1 (bypass) mode. The word stream from the TX progresses to the RX, and the order of the words is not impacted in this scenario. Initial don't cares in the RX are disregarded.
In scenario (B), the byte serializer is set to the x2 (double width) mode. The word steam from the TX progresses to the RX and aligns ideally after the initial don't cares are disregarded. The position of LSB1 and MSB1 are correctly aligned to set the pattern for subsequent words.
In scenario (C), the byte serializer is also set to the x2 (double width) mode. However, LSB1 occupies an incorrect position, which forces the remaining words to misalign correspondingly. Intel provides RTL code example that can resolve the byte ordering misalignment in the FPGA core. For more information about the example code, refer to the Byte ordering correction code.
The RTL block is gated by reset_n and rx_syncstatus, and must be clocked by rx_clockout. The rx_parallel_data signal is the primary input for the block monitors and must be accompanied by rx_datak which captures the location of the control character. In Ethernet applications, K28.5 is a frequently used control character. The objective of the RTL is to bind the control character to the LSB.
From the protocol perspective, this is the logic that eliminates the misalignment. When rx_parallel_data enters the byte ordering RTL with the correct alignment, it is automatically bypassed. Because the RTL logic is constantly searching for the control character, it continuously binds the same control character to the LSB. The continuous and real time correction is required for (SI/PI), PDN, and thermal conditions that produce the byte ordering misalignment.
This implements the required PLLs, reset, and supporting IPs to complete the transceiver design.