L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 10/05/2023
Document Table of Contents Clock Generation Block (CGB)

Intel® Stratix® 10 devices include the following types of clock generation blocks (CGBs):

  • Master CGB
  • Local CGB

Transceiver banks have two master CGBs. The master CGB divides and distributes bonded clocks to a bonded channel group. The master CGB also distributes non-bonded clocks to non-bonded channels across the x6/x24 clock network.

Each transceiver channel has a local CGB. The local CGB divides and distributes non-bonded clocks to the corresponding PCS and PMA blocks.