L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

6.6.1. Channel Reconfiguration

  1. If you have background calibration enabled, disable it by setting channel offset address 0x542[0] to 0x0.
    You disabled it successfully if 0x542[0] = 0x0, 0x481[2] = 0x0, or reconfig_waitrequest is low.
  2. Pause Traffic: Assert the required channel resets (if necessary). Refer to the section Recommendations for Dynamic Reconfiguration for details on which resets need to be asserted. If you are reconfiguring across data rates or protocol modes or enabling/disabling PRBS, place the channels in reset.
  3. Modify: Perform the necessary reconfiguration using the flow described in Direct Reconfiguration Flow, Native PHY or PLL IP Guided Reconfiguration Flow, and Reconfiguration Flow for Special Cases.
  4. Re-align: Request recalibration, if reconfiguration involved data rate or protocol mode change, and wait for the calibration to complete. Calibration is complete when tx/rx/pll_cal_busy is deasserted. For more details about calibration registers and the steps to perform recalibration, refer to the Calibration chapter. If you reconfigured:
    1. TX simplex channel for data rate change—you must recalibrate the channel TX.
    2. RX simplex channel for data rate change—you must recalibrate the channel RX.
    3. Duplex channel for data rate change—you must recalibrate the channel RX, followed by the TX.
  5. Return Control: After you have performed all necessary reconfiguration, return the internal configuration bus access to PreSICE with a direct write of 0x01 to offset address 0x000. You may have to reconfigure the PMA analog parameters of the channels. Refer to the Changing PMA Analog Parameters section for more details.
  6. Resume Traffic: Deassert analog resets followed by digital resets. Refer to "Recommendations for Dynamic Reconfiguration" for details on the resets that needs to be deasserted.
  7. If desired, enable background calibration by setting channel offset address 0x542[0] to 0x1.
    • The background calibration feature is only available for H-tile production devices starting with Intel® Quartus® Prime Design Suite 18.1 and if the data rate is >= 17.5 Gbps.
    • Refer to Background Calibration for more information.
Note: You cannot merge multiple reconfiguration interfaces across multiple IP blocks (merging independent instances of simplex TX/RX into the same physical location or merging separate CMU PLL and TX channel into the same physical location) when you enable the optional reconfiguration logic registers.

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