188.8.131.52.5. 10GBASE-R Mode
In 10GBASE-R mode, the RX Core FIFO operates as a clock compensation FIFO. When the block synchronizer achieves block lock, data is sent through the FIFO. Idle ordered sets (OS) are deleted and Idles are inserted to compensate for the clock difference between the RX low speed parallel clock and the FPGA fabric clock (±100 ppm for a maximum packet length of 64,000 bytes).
Idle OS Deletion
Deletion of Idles occurs in groups of four OS (when there are two consecutive OS) until the rx_fifo_rd_pfull flag deasserts. Every word—consisting of a lower word (LW) and an upper word (UW)—is checked for whether it can be deleted by looking at both the current and previous words.
If only one word is deleted, data shifting is necessary because the datapath is two words wide. After two words have been deleted, the FIFO stops writing for one cycle and a synchronous flag (rx_control) appears on the next block of 8-byte data. There is also an asynchronous status signal rx_enh_fifo_del, which does not go through the FIFO.
Idle insertion occurs in groups of 8 Idles when the rx_enh_fifo_pempty flag is deasserted. Idles can be inserted following Idles or OS. Idles are inserted in groups of 8 bytes. Data shifting is not necessary. There is a synchronous status rx_enh_fifo_insert signal that is attached to the 8-byte Idles being inserted.