L- and H-Tile Transceiver PHY User Guide

ID 683621
Date 7/20/2022
Public
Document Table of Contents

2.4.4.1.3. PRBS Generator and Verifier

The PRBS generator generates a self-aligning pattern and covers a known number of unique sequences. Because the PRBS pattern is generated by a Linear Feedback Shift Register (LFSR), the next pattern can be determined from the previous pattern. When the PRBS verifier receives a portion of the received pattern, it can generate the next sequence of bits to verify whether the next data sequence received is correct.

The PRBS generator and verifier can only be used with either a 10-bit or 64-bit PCS-PMA interface. PRBS9 is available in 10-bit and 64-bit PCS-PMA widths. All other PRBS patterns are available in 64-bit PCS-PMA width only. Because the FPGA fabric-PCS interface must run within the recommended speed range of the FPGA core, ensure that you are using the correct PCS-PMA width for your corresponding datarate so as not to go above this range.

Table 93.   PRBS Supported Polynomials and Data WidthsUse the 10-bit mode of PRBS9 when the datarate is lower than 3 Gbps.
Pattern Polynomial 64-Bit 10-Bit Best Use
PRBS7 G(x) = 1+ x6 + x7 Yes Use PRBS7 and PRBS9 to test transceiver links with linear impairments, and with 8B/10B.
PRBS9 G(x) = 1+ x5 + x9 Yes Yes
PRBS15 G(x) = 1+ x14 + x15 Yes Use PRBS15 for jitter evaluation.
PRBS23 G(x) = 1+ x18 + x23 Yes Use PRBS23 or PRBS31 for jitter evaluation (data-dependent jitter) of non-8B/10B links, such as SDH/SONET/OTN jitter testers. Most 40G, 100G, and 10G applications use PRBS31 for link evaluation.
PRBS31 G(x) = 1+ x28 + x31 Yes

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